SPDIF clock recoveryStarted by 1 year ago●7 replies●latest reply 1 year ago●290 views
I am working on a project to use a digital front end for my triamp. I am struggling to work out how to decode an incoming spdif audio signal. Is a phase locked loop the way to go and what is the method for including the time clock within the processor. I am looking to use a teensy4.1 board with an arm processor so I am not sure how to integrate the clock recovered with a fast processor.
Then there is the data recovery from BMC format. I have looked at the xor logic and was thinking whether each sample could be taken at approx midway through the bit where the signal would be stable.
Any help would be appreciated.
I'm not clear as to exactly what you're trying to build and its architecture, but the only practical way to decode SPDIF is with a SPDIF receiver. Either a standalone part from TI, ADI, Cirrus, AKM or integrated in to a DSP chip like ADI's SigmaDSP or xMOS. (good luck finding chips though)
If this is a one off project you can find boards that are SPDIF/ToS to I2S out there.
No I haven't been very clear.
I built a triamp which includes a signal filter to provide the three frequency bands, high, medium and low. Each signal is then attenuated and input to a separate stereo amplifier. It is all analogue.
What I would like to do is use a cd transporter with a SPDIF output, feed the stereo signal through a digital filter to provide the three frequency bands, use a digital attenuator for each channel, followed by a dac for each channel then inputs to the three stereo amps.
To build the digital filter I need to have a SPDIF generator along with an spdif receiver and converter to a usable code for testing the filter.
It was my intention to build all equipment from scratch using readily available processors which are not likely to be obsolete in a short time.
I have experience in assembly code and wrote everything for my triamp in it for the attenuators using an optical encoder which was 20 pages long.
It may be a very difficult project but I would like to try.
My suggestion would be to start with off the shelf hardware so you can gain some experience and then work towards rolling your own. The lack of audio parts (ADC, DAC, DSP), both from the AKM fire and the sh!t-show that the semiconductor supply chain has become, makes it really tough to "get a few parts and play around"
I was going to suggest https://freedsp.github.io/ but looks the audio DSP board is out of stock. https://www.minidsp.com/ makes things you could use. Or get an eval board for https://www.analog.com/en/products/adau1452.html#p... from Digikey/Mouser.
There's also HW options for RPi, for example https://www.hifiberry.com/
Lastly, if *really* want to torture yourself with an extremely powerful solution look at https://www.analog.com/en/design-center/evaluation... Would only suggest this option if you've worked on similar types of embedded DSP in the past.
For completeness I'll throw "FPGA" out there, again not a suggested path unless you've worked with them in the past.
Thanks for your help, have had a quick look at your links, will look at them in more detail now.
I had suggested a little FPGA for this but do not know how familiar you are with that. S/PDIF is a piece of cake in there, so is clock recovery and jitter attenuation in order to achieve highly stable internal clock rates. For just getting an input to drive own analoge hardware with, a ready built module might be better. The Bay and ALI has some chinese pcbs to receive S/PDIF and I2S directly and derive analog audio via RCA jacks. These might be a godd starting point and are priced around $10,-. There are also devices with aluminum housing providing shielding around $20,- . Forthermore there are some better PCBs having also AES EBU input and output and provide XLR-compatible symmetrical audio out.
No I'm not familiar with FPGA but will check it out. Thanks for the info.
I am looking at using my analogue signal generator with an adc to produce an spdif signal at any frequency for testing my receiver (hopefully when built).