Why are there tones for DC input in sigma delta modulator?
Given Vref varying from +1 to -1, DC input = 0V, I see a peak at Fs/2 in the spectrum
How does randomly adding noise to the input signal help in overcoming tones?
Did you look at the modulator output? 1st-order modulators produce cycles for constant-voltage input: 011011011011011011011 (for input of 2/3) or 010101010101 (for input of 1/2) or 01010110101101011010 (for input of 0.6)
In general if the input ranges from 0 to 1 and can be written as some rational number p/q then the 1st-order modulator output is periodic with period q, and therefore you'll get tones. The only way to avoid tones is for the input to be not close to rational numbers p/q with small q. (which doesn't really happen)
Adding dithering noise spreads the spectrum; you still have more or less the same energy that was present in the 1st-order modulator tones, but it is spread over a wider frequency range. Second-order and higher modulators do this automatically.
sample Python code to see this:
def dsmod(rho, n): acc = 0 for _ in xrange(n): acc += rho out = 1 if acc >= 1 else 0 acc -= out yield out >>> list(dsmod(0.5,20)) [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1] >>> list(dsmod(0.6,20)) [0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0]
Adding noise to any digital modulation process with large harmonic spurs on its output is effective at spreading the spurs' energy to meet FCC testing spurious output requirements. We did that at work for a VOR signal generator and it was quite effective. (One might then argue that the FCC testing requirements should rely more on averaging and not peaks, but it is what it is.)
"(One might then argue that the FCC testing requirements should rely more on averaging and not peaks, but it is what it is.)"
One might argue in reply that in a portion of the spectrum that's assigned to traditional narrowband services, one honkin' big tone sticking up in the middle of things may not affect most users, but there'll certainly be one user who's severely affected.
I worked at a place where we had one customer who was seeing interference at one frequency from one of our microprocessor clocks. They were big enough that we built a board just for them that had the frequency pushed over to the next-lower standard crystal frequency, with special software that loaded different values in all the relevant counters to make it work.
You can buy spread-spectrum clocks for microprocessors and other uses just for that reason (see: http://www.ti.com/clock-and-timing/generators/spre...)
Thank you so much for the reply. But the doubt I have is very basic. When I have Vref ranging from -1 to 1 and input is DC 0 V, the output is 0101010101. This is passed through a Kaiser window and absolute value of FFT is taken. Here I see a spike at Fs/2. I don't understand this. When the input is 0.5V, I see 4 spikes and so on. Could you please explain this?
Attaching my code
Fs = 4096;
dt = 1/Fs;
t = 0:dt:1-dt;
%x = 1.5*(sin(2*pi*50.5*t))+.08*randn(size(t));
x = 0*(1+ 0*t)
l = length(x);
u(1) = 0.1
for i = 1:l
y(i) = 2;
y(i) = -2;
e(i) = x(i) - y(i);
u(i+1)= u(i) + e(i);
x2 = y.*kaiser(length(y),13)'
X1 = db(abs(fft(x)));
Y1 = db(abs(fft(x2)));
X2 = fft(x2)
Basically I am new to DSP and trying to understand it through experiments. I would appreciate if you could suggest me any good material to understand this.
To understand, forget for a moment the FFT results. Look at the signal itself and see if you understand its behavior. What is the period of the signal 0101010101010101? What about 00010001000100010001? How does this compare with the sampling time? What would you expect for frequency content?
The period of the signal 01010101 is 2 and that of 00010001 is 4. the frequency of 010101 is twice that of 000100010001. The sampling time of 010101 is half that of 000100010001
You may want to start by doing some google searches of what delta sigma modulators are and how they work. A quantized signal is going to be equal to the input signal plus some error. A DS modulator acts to low pass filter the input and high pass filter the error. However, we cannot simply filter out the error, because the output is quantized, the error has to exist. Instead the error spectrum is shaped roughly following the shape of the high pass filter.
I’ve found lots of great information on dithering online, so don’t be shy to do some searching of your own. Basically, it’s supposed to change peaks in the error spectrum into an overall noise floor.
To more directly answer your first questions - you are experiencing idle tones. These are common in sigma-delta modulators, especially low orders. This is because the modulators get 'stuck' into cyclical patterns when there are no differences in the input to kick them out. A first-order system is more likely to fall into repetitive cycles because there is less filtering and delay to try to 'break up' the patterns; you'll see a decrease as you go to 2nd order, but there will still be patterns.
There are several solutions or at least ameliorations. First is to go to multi-bit output. This reduces the quantization noise which cause the the idle tones in the first place. Second is to go to higher orders, for reasons explained above. Next is to actually add DC to the input. This isn't a happy solution, because it makes the output unbalanced in saturation and reduces output range on one side. But, if the tone is sitting at high frequency, adding DC can push the town out of band where it is filtered out by the anti-aliasing or anti-imaging filtering.
Google searches: SDM idle tones, SDM chaotic behavior, SDM quantization