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DSP RTL Library (DRL): An Open Source Verilog/SystemVerilog Approach

Started by ahmedshahein 3 weeks ago2 replieslatest reply 2 weeks ago99 views
I am delighted to share with my passion in DSP by releasing the DSP-RTL-Library or (DRL) on GitHub. The library provides various standard DSP components such as; filters (FIR, MAC, CIC, PPD, PPI ...) and signal generators (NCO and CORDIC) and more to come. The RTL is developed in Verilog-2001, the test-benches are developed in SystemVerilog, and the reference models are developed in Octave. I was keen to make the code quite parameterizable so that the designer can manipulate and investigate as much configuration parameters as possible. The library is provided with a Bash script which supports a lot of automation is generating the desired RTL and verification test suite as well.

Check the documentation and the README for getting started.

Your constructive feedback is quite welcomed.

Have fun!

GitHub Link

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Reply by gretzteamAugust 30, 2019

Hi,

This is pretty cool! Have you thought of using cocotb for the testbench / bit-accurate modeling?

https://github.com/cocotb/cocotb

https://cocotb.readthedocs.io/en/latest/

It's extremely powerful and would allow to keep the testbench and modeling code in the same language (python) and avoid having to deal with PLI / fileIO. I do a lot of this DSP stuff and this has proven to be extremely powerful.

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Reply by ahmedshaheinAugust 30, 2019

Thanks a lot for the remark, I will definitely look into it and get back to you.

It is already has a standard test-bench loading stimuli and response files (generates from Octave models) and compare it to RTL output to ensure bit-trueness.

I am also working on another project for Verification.

Keep you posted.

Re