ASIC Digital Designer

Re: The size of an FIR filter for PDM-PCM conversion

Reply posted 2 months ago (07/17/2020)
I would approach this as a frequency domain problem and come up with the frequency response that you want (using whatever filter type that suits you: FIR, IIR,...
Farrow is just generic structure for implementing polynomials (including linear interp).Now the frequency response of polynomial based filter doesn't improve much...
This isn't accurate. The Farrow structure is generic and can implement any polynomial type and order. The coefficients determine which polynomial is implemented:...

Re: Digital Filters that have prescribed phase shift

Reply posted 4 months ago (05/30/2020)
There is a pretty good write-up here about the two path allpass Hilbert transform.http://yehar.com/blog/?p=368

Re: Impulse response of CIC filter

Reply posted 8 months ago (01/22/2020)
I'm not sure what you mean...Start from the full FIR filter and pick every N samples...?

Re: Impulse response of CIC filter

Reply posted 8 months ago (01/15/2020)
I would ignore the CIC filter part and read up about standard FIR filters and their polyphase implementation when used for decimation.CIC is just a clever recursive...

Re: Impulse response of CIC filter

Reply posted 8 months ago (01/15/2020)
if the yaxis was in 'dB' it would even look like a normal frequency response! 

Re: Impulse response of CIC filter

Reply posted 8 months ago (01/15/2020)
Those are the frequency responses of each individual 'polyphase' of the full FIR filter. The frequency response you're most likely interested in is that of the full...

Re: #CIC filters and testing them

Reply posted 8 months ago (01/12/2020)
Hi,I think this only has to do with the "phase" at which you clock the differentiators relative to the first non zero input going into the integrators. Changing...

Re: Guaranteed stable sliding Goertzel implementation

Reply posted 9 months ago (12/09/2019)
Hi Rick,I wonder how this is even allowed to be a 'paper':Denis A. Gudovskiy and Lichung Chu, "An Accurate and Stable Sliding DFT Computed by a Modified CIC Filter", IEEE...

Re: Delta Sigma Modulator Decimation output

Reply posted 11 months ago (10/19/2019)
All those filters should have exactly the same frequency response (according to your description). Recursive vs non-recursive vs polyphase using stages vs polyphase...

Re: CIC filter using prune width calculation

Reply posted 11 months ago (10/18/2019)
This is discussed in the original Hogenauer paper. If I remember right some of the stages benefit from rounding, but for others floor() was just as good (or something...

Re: CIC filter using prune width calculation

Reply posted 11 months ago (10/17/2019)
1 lsb error is probably what you should expect. You'll always get up to 1 lsb since there is truncation. 

Re: CIC filter using prune width calculation

Reply posted 11 months ago (10/17/2019)
I haven't looked a Rick'code but you certainly don't need more bits than 43 at any given stage. I would guess a negative Bj value is really a 0, so here your first...
All the suggestions so far would work (skip/repeat sample, linear interpolation, quadratic, cubic...). Those are all polynomial filters of different orders. They...
Hi,This is pretty cool! Have you thought of using cocotb for the testbench / bit-accurate modeling?https://github.com/cocotb/cocotbhttps://cocotb.readthedocs.io/en/latest/It's...

Re: Fixed Point Library for Python

Reply posted 1 year ago (06/11/2019)
This is extremely helpful. I've been a Matlab user for many years and the 'fi()' library is tremendously helpful in getting things done quickly avoiding stupid mistakes....

Re: Fixed point filter gain

Reply posted 2 years ago (03/07/2019)
DC gain?sum(coeff)?

Re: Arbitrary Resampling issue : 30.72 MHz to 20 MHz

Reply posted 2 years ago (06/07/2018)
Hi, Imagine a case where you cannot control the input rate. Say the data comes from an ADC running at a fixed rate from its own oscillator. In such a case all you...

Re: Arbitrary Resampling issue : 30.72 MHz to 20 MHz

Reply posted 2 years ago (06/07/2018)
Hi Kaz,This has nothing to do with FPGA or ASIC implementation. The problem of irrational rate conversion happens all the time. The case you highlighted is one of...

Re: Arbitrary Resampling issue : 30.72 MHz to 20 MHz

Reply posted 2 years ago (06/06/2018)
Hi,The way I think of it is as follow:(1) integer: ...(2) fractional: any number that can be represented as a fraction of integers...like the case here.(3) irrational:...

Re: Arbitrary Resampling issue : 30.72 MHz to 20 MHz

Reply posted 2 years ago (06/06/2018)
Hi,Depending on your hardware constraints and filter response requirements, one efficient structure for this is the so-called transposed farrow structure. It typically...

Re: Optimal Filter lineup selection

Reply posted 3 years ago (05/16/2017)
Like everybody said, you need to define what is optimal to you (area, power, complexity, reusability...).But big picture, you want to decimate in multiple stages...

Re: Back to back CIC filters

Reply posted 3 years ago (04/21/2017)
Yes you can definitely do this. But as Tim pointed out in one answer, make sure you get the wordlength right. Draw the two filters in cascade, with the wordlength at...
Hi,It's interesting how you quickly start to get errors once the magnitude is not defined across the whole bandwidth. For example, say you only have magnitude data...
Hi,Actually, as I was posting this is occurred to me that the Hilbert transform probably wants to see the complete spectrum (not just positive frequencies...).Fixed...
Hi,I'm trying to calculate the minimum phase response of a given magnitude response (measured). It is well known that there is a 1:1 relationship between the magnitude...

Re: Can we paralleize the integrator stage of CIC?

Reply posted 3 years ago (04/07/2017)
I wouldn't go that far...To me it's just an observation that the recursive structure of those filters is not always the preferred one depending on sampling rate,...

Re: Can we paralleize the integrator stage of CIC?

Reply posted 3 years ago (04/07/2017)
You are correct, polyphase CIC is just a fancy name for FIR filter. Since it's decimating, you can use all the tricks that exists for decimating FIR filter, one...

Re: Can we paralleize the integrator stage of CIC?

Reply posted 3 years ago (04/07/2017)
Then typically what people do is either:1) split the CIC filter into multiple CIC stages. The constraints on the first stage will be less stringent so you can get...

Re: Can we paralleize the integrator stage of CIC?

Reply posted 3 years ago (04/07/2017)
Make sure you're using delaying integrator so that the critical path is only that of one adder. Many CIC filters are drawn using non-delaying integrator, creating...

Re: PDM asynchronous sample rate conversion

Reply posted 3 years ago (03/24/2017)
Without having run the math, I feel like a zero-order hold filter should be good enough at this oversampling ratio. That would be much simpler as you don't need...

Re: PDM asynchronous sample rate conversion

Reply posted 3 years ago (03/23/2017)
Hi,There are indeed a few tricks you can play since your data is already oversampled. It isn't ideally oversampled because of the sigma-delta noise, but you can...

Re: Downsampling from 2.0 MHz to 192kHz

Reply posted 4 years ago (10/26/2016)
Hi,First I do agree with all the replies so far: something seems odd with the problem statement from the OP. Now assuming that the OP really needs to decimate by...

Re: Downsampling from 2.0 MHz to 192kHz

Reply posted 4 years ago (10/25/2016)
So you're trying to decimate by:2e6 / 192e3 = 10.4167First I would question the requirements - is this really necessary? Can you change the system clocking so this...

Re: Coherent Sampling (Very Brief and Simple)

Reply posted 4 years ago (06/22/2016)
Hi Tim,Can you elaborate on this?what is the input to the ADC in this case? What is the goal here? Seems interesting but I can't quite figure out the system. 

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