Steve Maslen (@MixedSignal)
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
Built around modest FPGA hardware, this post presents a practical test-bed for evaluating high-speed, low-latency feedback controllers. It covers ADC/DAC specifications, basic and arbitrary test signals, and an IFFT-based generator that can produce thousands of simultaneous tones for rapid Bode, phase, and latency measurements. The article also compares two IFFT strategies, explains turbo sampling, and shows open- and closed-loop test configurations.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.
- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
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