## Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

Additional...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Design IIR Filters Using Cascaded Biquads

This article shows how to implement a Butterworth IIR lowpass filter as a cascade of second-order IIR filters, or biquads. We’ll derive how to calculate the coefficients of the biquads and do some examples using a Matlab function biquad_synth provided in the Appendix. Although we’ll be designing Butterworth filters, the approach applies to any all-pole lowpass filter (Chebyshev, Bessel, etc). As we’ll see, the cascaded-biquad design is less sensitive to coefficient...

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## An Efficient Linear Interpolation Scheme

This blog presents a computationally-efficient linear interpolation trick that requires at most one multiply per output sample.

Background: Linear Interpolation

Looking at Figure 1(a) let's assume we have two points, [x(0),y(0)] and [x(1),y(1)], and we want to compute the value y, on the line joining those two points, associated with the value x.

Figure 1: Linear interpolation: given x, x(0), x(1), y(0), and y(1), compute the value of y. ...

## Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...

## Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...

## Canonic Signed Digit (CSD) Representation of Integers

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values. Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}. Thus, for example, the binary value 1 1...

## Matlab Code to Synthesize Multiplierless FIR Filters

This article presents Matlab code to synthesize multiplierless Finite Impulse Response (FIR) lowpass filters.

A filter coefficient can be represented as a sum of powers of 2. For example, if a coefficient = decimal 5 multiplies input x, the output is $y= 2^2*x + 2^0*x$. The factor of $2^2$ is then implemented with a shift of 2 bits. This method is not efficient for coefficients having a lot of 1’s, e.g. decimal 31 = 11111. To reduce the number of non-zero...

## Design IIR Filters Using Cascaded Biquads

This article shows how to implement a Butterworth IIR lowpass filter as a cascade of second-order IIR filters, or biquads. We’ll derive how to calculate the coefficients of the biquads and do some examples using a Matlab function biquad_synth provided in the Appendix. Although we’ll be designing Butterworth filters, the approach applies to any all-pole lowpass filter (Chebyshev, Bessel, etc). As we’ll see, the cascaded-biquad design is less sensitive to coefficient...

## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

Additional...

## An Efficient Linear Interpolation Scheme

This blog presents a computationally-efficient linear interpolation trick that requires at most one multiply per output sample.

Background: Linear Interpolation

Looking at Figure 1(a) let's assume we have two points, [x(0),y(0)] and [x(1),y(1)], and we want to compute the value y, on the line joining those two points, associated with the value x.

Figure 1: Linear interpolation: given x, x(0), x(1), y(0), and y(1), compute the value of y. ...

## Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

## Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...

## Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## Dealing With Fixed Point Fractions

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## A poor man's Simulink

Glue between Octave and NGSPICE for discrete- and continuous time cosimulation (download) Keywords: Octave, SPICE, Simulink

IntroductionMany DSP problems have close ties with the analog world. For example, a switched-mode audio power amplifier uses a digital control loop to open and close power transistors driving an analog filter. There are commercial tools for digital-analog cosimulation: Simulink comes to mind, and mainstream EDA vendors support VHDL-AMS or Verilog-A in their...

## Design IIR Filters Using Cascaded Biquads

This article shows how to implement a Butterworth IIR lowpass filter as a cascade of second-order IIR filters, or biquads. We’ll derive how to calculate the coefficients of the biquads and do some examples using a Matlab function biquad_synth provided in the Appendix. Although we’ll be designing Butterworth filters, the approach applies to any all-pole lowpass filter (Chebyshev, Bessel, etc). As we’ll see, the cascaded-biquad design is less sensitive to coefficient...

## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

Additional...

## An Efficient Linear Interpolation Scheme

This blog presents a computationally-efficient linear interpolation trick that requires at most one multiply per output sample.

Background: Linear Interpolation

Looking at Figure 1(a) let's assume we have two points, [x(0),y(0)] and [x(1),y(1)], and we want to compute the value y, on the line joining those two points, associated with the value x.

Figure 1: Linear interpolation: given x, x(0), x(1), y(0), and y(1), compute the value of y. ...

## A poor man's Simulink

Glue between Octave and NGSPICE for discrete- and continuous time cosimulation (download) Keywords: Octave, SPICE, Simulink

IntroductionMany DSP problems have close ties with the analog world. For example, a switched-mode audio power amplifier uses a digital control loop to open and close power transistors driving an analog filter. There are commercial tools for digital-analog cosimulation: Simulink comes to mind, and mainstream EDA vendors support VHDL-AMS or Verilog-A in their...

## Dealing With Fixed Point Fractions

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...

## Canonic Signed Digit (CSD) Representation of Integers

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values. Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}. Thus, for example, the binary value 1 1...

## Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

## Matlab Code to Synthesize Multiplierless FIR Filters

This article presents Matlab code to synthesize multiplierless Finite Impulse Response (FIR) lowpass filters.

A filter coefficient can be represented as a sum of powers of 2. For example, if a coefficient = decimal 5 multiplies input x, the output is $y= 2^2*x + 2^0*x$. The factor of $2^2$ is then implemented with a shift of 2 bits. This method is not efficient for coefficients having a lot of 1’s, e.g. decimal 31 = 11111. To reduce the number of non-zero...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator