Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

Steve Maslen November 22, 2018

This article will look at a design approach for feedback controllers featuring  low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.    

Fig 1. Making a Transmission Line, with the Circuit Emulator

 

Additional...


Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

Steve Maslen July 9, 2018

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.    

Fig 1. The evaluation platform

Additional design...


Design IIR Filters Using Cascaded Biquads

Neil Robertson February 11, 2018
This article shows how to implement a Butterworth IIR lowpass filter as a cascade of second-order IIR filters, or biquads.  We’ll derive how to calculate the coefficients of the biquads and do some examples using a Matlab function biquad_synth provided in the Appendix.  Although we’ll be designing Butterworth filters, the approach applies to any all-pole lowpass filter (Chebyshev, Bessel, etc).  As we’ll see, the cascaded-biquad design is less sensitive to coefficient...

Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

Steve Maslen January 5, 20187 comments
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality. 

Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator


An Efficient Linear Interpolation Scheme

Rick Lyons December 27, 201723 comments

This blog presents a computationally-efficient linear interpolation trick that requires at most one multiply per output sample.

Background: Linear Interpolation

Looking at Figure 1(a) let's assume we have two points, [x(0),y(0)] and [x(1),y(1)], and we want to compute the value y, on the line joining those two points, associated with the value x. 

       Figure 1: Linear interpolation: given x, x(0), x(1), y(0), and y(1), compute the value of y. ...


Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

Steve Maslen November 14, 2017
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with  application  examples will be maintained on the project website here.

Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Steve Maslen October 10, 2017
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with  application  examples will be maintained on the project website. 

Canonic Signed Digit (CSD) Representation of Integers

Neil Robertson February 18, 2017

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients.  I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values.  Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}.  Thus, for example, the binary value 1 1...


Matlab Code to Synthesize Multiplierless FIR Filters

Neil Robertson October 31, 20163 comments

This article presents Matlab code to synthesize multiplierless Finite Impulse Response (FIR) lowpass filters.

A filter coefficient can be represented as a sum of powers of 2.  For example, if a coefficient = decimal 5 multiplies input x, the output is $y= 2^2*x + 2^0*x$.  The factor of $2^2$ is then implemented with a shift of 2 bits.  This method is not efficient for coefficients having a lot of 1’s, e.g. decimal 31 = 11111.  To reduce the number of non-zero...


Dealing With Fixed Point Fractions

Mike January 5, 20163 comments

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow.  If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions.  When integers overflow, they lose data off the most significant bits.  When fractions overflow, they lose data off...


A poor man's Simulink

Markus Nentwig January 24, 20153 comments

Glue between Octave and NGSPICE for discrete- and continuous time cosimulation (download) Keywords: Octave, SPICE, Simulink

Introduction

Many DSP problems have close ties with the analog world. For example, a switched-mode audio power amplifier uses a digital control loop to open and close power transistors driving an analog filter. There are commercial tools for digital-analog cosimulation: Simulink comes to mind, and mainstream EDA vendors support VHDL-AMS or Verilog-A in their...


Dealing With Fixed Point Fractions

Mike January 5, 20163 comments

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow.  If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions.  When integers overflow, they lose data off the most significant bits.  When fractions overflow, they lose data off...


Design IIR Filters Using Cascaded Biquads

Neil Robertson February 11, 2018
This article shows how to implement a Butterworth IIR lowpass filter as a cascade of second-order IIR filters, or biquads.  We’ll derive how to calculate the coefficients of the biquads and do some examples using a Matlab function biquad_synth provided in the Appendix.  Although we’ll be designing Butterworth filters, the approach applies to any all-pole lowpass filter (Chebyshev, Bessel, etc).  As we’ll see, the cascaded-biquad design is less sensitive to coefficient...

An Efficient Linear Interpolation Scheme

Rick Lyons December 27, 201723 comments

This blog presents a computationally-efficient linear interpolation trick that requires at most one multiply per output sample.

Background: Linear Interpolation

Looking at Figure 1(a) let's assume we have two points, [x(0),y(0)] and [x(1),y(1)], and we want to compute the value y, on the line joining those two points, associated with the value x. 

       Figure 1: Linear interpolation: given x, x(0), x(1), y(0), and y(1), compute the value of y. ...


Matlab Code to Synthesize Multiplierless FIR Filters

Neil Robertson October 31, 20163 comments

This article presents Matlab code to synthesize multiplierless Finite Impulse Response (FIR) lowpass filters.

A filter coefficient can be represented as a sum of powers of 2.  For example, if a coefficient = decimal 5 multiplies input x, the output is $y= 2^2*x + 2^0*x$.  The factor of $2^2$ is then implemented with a shift of 2 bits.  This method is not efficient for coefficients having a lot of 1’s, e.g. decimal 31 = 11111.  To reduce the number of non-zero...


DSP Algorithm Implementation: A Comprehensive Approach

Sami Aldalahmeh April 13, 20116 comments

As DSP engineers, ultimately we are required to design and implement specific DSP algorithms. The first step is to make a choice on which algorithm to use, e.g. for filtering should we use FIR or IIR. Then we can go a little bit deeper into the,  high level, implementation details, e.g. use the symmetry in FIR filter to reduce complexity. When the algorithm is clear, the first step is to test and simulate the algorithm in a high level language like MATLAB.

After we reach confidence in...


Weighted least-squares FIR with shared coefficients

Markus Nentwig May 23, 2012

FIR design with arbitrary routing between delay line and coefficient multipliers.

Includes a commented implementation of a generic IRLS FIR design algorithm.

Introduction: Reverse Engineering

While looking for numerical IIR filter optimization, a Matlab program in [1] for the design of FIR filters caught my attention. The equations looked familiar, sort of, but on closer examination the pieces refused to fit together. Without the references, it took about two evenings to sort out how it...


'z' as in 'Zorro': Frequency Masking FIR

Markus Nentwig October 2, 2012

An efficient way to implement FIR filters. Matlab / Octave example included. Keywords: Frequency masking FIR filter implementation

Introduction

An "upsampled" FIR filter uses multiple-sample delays between the taps, compared to the unity delays in a conventional FIR filter. The resulting frequency response has steeper edges, but contains periodic images along the frequency axis (Fig. 1). Due to the latter, it is typically not too useful on its own.

Figure 1: Conventional and 'upsampled'...

Accelerating Matlab DSP Code on the GPU

Seth March 25, 20102 comments

Intrigued by GPUs, I've spent a few days testing out Jacket, an interface that lets you accelerate MATLAB (my favorite, if frustrating language) on NVIDIA GPUs. It's definitely got some caveats. But it was really easy to accelerate my code. And the results were impressive. So I thought I'd put up a few simple DSP-related benchmarks I created and ran on my laptop (a Macbook Air with NVIDIA GeForce 9400M graphics card). The m-files for the two functions I benchmarked (2D FFT and 2D...


Canonic Signed Digit (CSD) Representation of Integers

Neil Robertson February 18, 2017

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients.  I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values.  Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}.  Thus, for example, the binary value 1 1...