Dear c6x: I have a question about XBUS of 6202. I use XBUS as asynchronous I/O. From the peripherals refrerence Guide I know...

Dear c6x: I have a question about XBUS of 6202. I use XBUS as asynchronous I/O. From the peripherals refrerence Guide I know i must use DMA to access the XBUS. But I can not access it. When i set the DMA destenation address as 0x80000000, it work well. But when i c

Hi everyone, Now I have a problem about TMS320C6203 XBUS in my project. I hope you can give me some advice and help. We...

Hi everyone, Now I have a problem about TMS320C6203 XBUS in my project. I hope you can give me some advice and help. We design a C6203 DSP system, with a fifo connecting to the DSP and the external interface by XBUS. The DSP reads data from fifo by xbus. And i kno

Hi,each friend,I have solved the problem. In my system, Internal XBUS arbiter must be enabled, If not,the DAM between FIFO...

Hi,each friend,I have solved the problem. In my system, Internal XBUS arbiter must be enabled, If not,the DAM between FIFO (connected to XBUS) and Internal memory will never happen.Pullup the XD10, all are right. Thanks to all friend,especially Jeff Brower! HuGuang

Any help with the following problem will be greatly appreciated. Our c6202 chip is Silicon revision 1.2. Question: We are...

Any help with the following problem will be greatly appreciated. Our c6202 chip is Silicon revision 1.2. Question: We are trying to boot the DSP via the XBUS. We are using a Motorola 8260 CPU as the host, and a 6202 DSP as the slave. Our XBUS interface is setup to run i

We are having trouble waking up the 6203 DSP from an XBUS boot process. We can see that the code has been loaded correctly through ...

We are having trouble waking up the 6203 DSP from an XBUS boot process. We can see that the code has been loaded correctly through the XBUS, but asserting DSP_INT doesn't appear to wake the DSP up. We know the code is OK because it runs if it's loaded through an emulator with Code Co

Hello everyone, I would like to know if the Xbus I/O port and the host port can be used together in a single system. To access the...

Hello everyone, I would like to know if the Xbus I/O port and the host port can be used together in a single system. To access the I/O port, the dsp would have to request the bus. But there is no HOLD and HOLDA timing information in the datasheet for synchronous FIFO access. So

Hi, all: We design a C6203 DSP system, with a FIFO connecting to the DSP and the external interface by XBUS. ...

Hi, all: We design a C6203 DSP system, with a FIFO connecting to the DSP and the external interface by XBUS. ---------------------------------------------------------------- XBus Some FFT data ~~~~~> | FIFO | =======> | C6203 | ------------------------

We connect a POWERPC to C6202's expansion bus. So we choose the XBUS boot mode for C6202. But when we finished initializing the ...

We connect a POWERPC to C6202's expansion bus. So we choose the XBUS boot mode for C6202. But when we finished initializing the C6202's external memory configuration registers -- EMIF CE0 space control through the XBUS interface, the CE0 is not active for refresh SDRAM. And the same

Hi, I'm looking for a way to get the contents of the log buffer filled by LOG_printf in a host processor. Please, anyone knows...

Hi, I'm looking for a way to get the contents of the log buffer filled by LOG_printf in a host processor. Please, anyone knows a way to do this? I think that it would be a kind of library that contains functions to read the log buffer from DSP via, for example, XBUS port.

Hi DSPers, I am using TMS320C6204 DSP to process data read from a FIFO. The FIFO is to be connected as glue less...

Hi DSPers, I am using TMS320C6204 DSP to process data read from a FIFO. The FIFO is to be connected as glue less interface through the Expansion bus of the DSP (in XCE3 space). The FIFO we are going to use is from IDT. Is the 6204 DSP compatible with the IDT FIFO

Dear friend: Hi, i know there are many experts on DSP in the discussion group. Now i get a hard problem. I hope you can give me...

Dear friend: Hi, i know there are many experts on DSP in the discussion group. Now i get a hard problem. I hope you can give me some advice and help. We design a DSP and FPGA system,with a FIFO to connect both. DSP: TMS320C6203 FPGA: XILINX Vertex XC2V3000 FIFO: IDT 72V36

Hi, I am presently developing under Code Composer (CCS) v2.2. I can compile, load and execute my code under Code Composer via...

Hi, I am presently developing under Code Composer (CCS) v2.2. I can compile, load and execute my code under Code Composer via the JTAG. What options do I need to include for my compiled code so that it boots and runs correctly when the ".out" file is download

Hi everyone, Now I have a problem about TMS320C6203 boot in my project. We design a C6203 DSP system, with a fifo connecting to the DSP and...

Hi everyone, Now I have a problem about TMS320C6203 boot in my project. We design a C6203 DSP system, with a fifo connecting to the DSP and the external interface by XBUS.Sometiems TMS320C6203 cannot boot correctly.Power on 20 times,one time TMS320C6203 cannot boot . when not boot,I connected the target board to the CCS with XDS560 JTAG emulator.Flash data read by CCS all are 0XFF.I have a re...

Dear All, Now I have a problem about TMS320C6203 boot in my project. We design a C6203 DSP system, with a fifo connecting to the DSP and the...

Dear All, Now I have a problem about TMS320C6203 boot in my project. We design a C6203 DSP system, with a fifo connecting to the DSP and the external interface by XBUS.Sometiems TMS320C6203 cannot boot correctly.Power on 20 times,one time TMS320C6203 cannot boot . when not boot,I connected the target board to the CCS with XDS560 JTAG emulator.Flash data read by CCS all are 0XFF.I have a reset...

Hi,everyone. there are three synchronous FIFO(133MHz) in our system. two link to EMIF of C6202, and one link to XBus of C6202....

Hi,everyone. there are three synchronous FIFO(133MHz) in our system. two link to EMIF of C6202, and one link to XBus of C6202. but the chip has not glueless FIFO interface. i want to interface to FIFO as SBSRAM,but the first access to SBSRAM requies an initial stert-up penalty