Stereophonic Amplitude-Panning: A Derivation of the "Tangent Law"

Rick Lyons

This article presents a derivation of the "Tangent Law"

A Brief Introduction To Romberg Integration

Rick Lyons

This article briefly describes a remarkable integration algorithm, called "Romberg integration." The algorithm is used in the field of numerical analysis but it's not so well-known in the world of DSP.

Evaluate Window Functions for the Discrete Fourier Transform

Neil Robertson

The Discrete Fourier Transform (DFT) operates on a finite length time sequence to compute its spectrum.  For a continuous signal like a sinewave, you need to capture a segment of the signal in order to perform the DFT.  Usually, you...

Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

Steve Maslen

This article will look at a design approach for feedback controllers featuring  low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to...

An IIR 'DC Removal' Filter

Rick Lyons

It seems to me that DC removal filters (also called "DC blocking filters") have been of some moderate interest recently on the dsprelated.com Forum web page. With that notion in mind I thought I'd post a little information, from Chapter 13 of my "Understanding DSP" book, regarding infinite impulse response (IIR) DC removal filters.

Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt. The project overview was discussed in the previous blog...

Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction

Jason Sachs

Last time, we talked about error correction and detection, covering some basics like Hamming distance, CRCs, and Hamming codes. If you are new to this topic, I would strongly suggest going back to read that article before this one. This time we...

Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Neil Robertson

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA.  This situation is shown in Figure 1.  Assuming your system has an...

Two Easy Ways To Test Multistage CIC Decimation Filters

Rick Lyons

This article presents two very easy ways to test the performance of multistage cascaded integrator-comb (CIC) decimation filters. Anyone implementing CIC filters should take note of the following proposed CIC filter test methods.

ADC Clock Jitter Model, Part 2 – Random Jitter

Neil Robertson

In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter.  Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered...