Ten Little Algorithms, Part 2: The Single-Pole Low-Pass Filter
Other articles in this series: Part 1: Russian Peasant Multiplication Part 2: The Single-Pole Low-Pass Filter Part 3: Welford’s Method (And Friends) Part 4: Topological Sort I’m writing this article in a room with a bunch of...
Simplest Calculation of Half-band Filter Coefficients
Half-band filters are lowpass FIR filters with cut-off frequency of one-quarter of sampling frequency fs and odd symmetry about fs/4 [1]*. And it so happens that almost half of the coefficients are zero. The passband and stopband bandwiths are equal, making these filters useful for decimation-by-2 and interpolation-by-2. Since the zero coefficients make them computationally efficient, these filters are ubiquitous in DSP systems. Here we will compute half-band coefficients using the window method. While the window method typically does not yield the fewest taps for a given performance, it is useful for learning about half-band filters. Efficient equiripple half-band filters can be designed using the Matlab function firhalfband [2].
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an...
Modeling Anti-Alias Filters
Digitizing a signal using an Analog to Digital Converter (ADC) usually requires an anti-alias filter, as shown in Figure 1a. In this post, we’ll develop models of lowpass Butterworth and Chebyshev anti-alias filters, and compute the time...
Plotting Discrete-Time Signals
A discrete-time sinusoid can have frequency up to just shy of half the sample frequency. But if you try to plot the sinusoid, the result is not always recognizable. For example, if you plot a 9 Hz sinusoid sampled at 100 Hz, you get the result shown in the top of Figure 1, which looks like a sine. But if you plot a 35 Hz sinusoid sampled at 100 Hz, you get the bottom graph, which does not look like a sine when you connect the dots. We typically want the plot of a sampled sinusoid to resemble its continuous-time version. To achieve this, we need to interpolate.
Simple Concepts Explained: Fixed-Point
IntroductionMost signal processing intensive applications on FPGA are still implemented relying on integer or fixed-point arithmetic. It is not easy to find the key ideas on quantization, fixed-point and integer arithmetic. In a series of...
Analytic Signal
In communication theory and modulation theory we always deal with two phases: In-phase (I) and Quadrature-phase (Q). The question that I will discuss in this blog is that why we use two phases and not more.
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Introduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
ADC Clock Jitter Model, Part 1 – Deterministic Jitter
Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold...
Bank-switched Farrow resampler
Bank-switched Farrow resampler Summary A modification of the Farrow structure with reduced computational complexity.Compared to a conventional design, the impulse response is broken into a higher number of segments. Interpolation accuracy is...
Stereophonic Amplitude-Panning: A Derivation of the "Tangent Law"
This article presents a derivation of the "Tangent Law"
A Brief Introduction To Romberg Integration
This article briefly describes a remarkable integration algorithm, called "Romberg integration." The algorithm is used in the field of numerical analysis but it's not so well-known in the world of DSP.
Evaluate Window Functions for the Discrete Fourier Transform
The Discrete Fourier Transform (DFT) operates on a finite length time sequence to compute its spectrum. For a continuous signal like a sinewave, you need to capture a segment of the signal in order to perform the DFT. Usually, you...
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to...
An IIR 'DC Removal' Filter
It seems to me that DC removal filters (also called "DC blocking filters") have been of some moderate interest recently on the dsprelated.com Forum web page. With that notion in mind I thought I'd post a little information, from Chapter 13 of my "Understanding DSP" book, regarding infinite impulse response (IIR) DC removal filters.
Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA
The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt. The project overview was discussed in the previous blog...
Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction
Last time, we talked about error correction and detection, covering some basics like Hamming distance, CRCs, and Hamming codes. If you are new to this topic, I would strongly suggest going back to read that article before this one. This time we...
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an...
Two Easy Ways To Test Multistage CIC Decimation Filters
This article presents two very easy ways to test the performance of multistage cascaded integrator-comb (CIC) decimation filters. Anyone implementing CIC filters should take note of the following proposed CIC filter test methods.
ADC Clock Jitter Model, Part 2 – Random Jitter
In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered...
Generating pink noise
In one of his most famous columns for Scientific American, Martin Gardner wrote about pink noise and its relation to fractal music. The article was based on a 1978 paper by Voss and Clarke, which presents, among other things, a simple...
Simulink-Simulation of SSB demodulation
Simulink-Simulation of SSB demodulation or modulation from the article “Understanding the ‘Phasing Method’ of Single Sideband Demodulation” by Richard Lyons Josef Hoffmann The article “Understanding the ‘Phasing Method’ of Single...
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an...
A Beginner's Guide to OFDM
In the recent past, high data rate wireless communications is often considered synonymous to an Orthogonal Frequency Division Multiplexing (OFDM) system. OFDM is a special case of multi-carrier communication as opposed to a conventional...
Second Order Discrete-Time System Demonstration
Discrete-time systems are remarkable: the time response can be computed from mere difference equations, and the coefficients ai, bi of these equations are also the coefficients of H(z). Here, I try to illustrate this remarkableness by converting a continuous-time second-order system to an approximately equivalent discrete-time system. With a discrete-time model, we can then easily compute the time response to any input. But note that the goal here is as much to understand the discrete-time model as it is to find the response.
Canonic Signed Digit (CSD) Representation of Integers
In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD...
An s-Plane to z-Plane Mapping Example
While surfing around the Internet recently I encountered the 's-plane to z-plane mapping' diagram shown in Figure 1. At first I thought the diagram was neat because it's a good example of the old English idiom: "A picture is worth a thousand...
Polyphase filter / Farrows interpolation
Hello, this article is meant to give a quick overview over polyphase filtering and Farrows interpolation. A good reference with more depth is for example Fred Harris' paper: http://www.signumconcepts.com/IP_center/paper018.pdf The task is as...
Music/Audio Signal Processing
Greetings,This is my blog from the point of view of a music/audio DSP research engineer / educator. It is informal and largely nontechnical because nearly everything I have to say about signal processing is (or will be) somewhere in my four-book...
Adventures in Signal Processing with Python
Author’s note: This article was originally called Adventures in Signal Processing with Python (MATLAB? We don’t need no stinkin' MATLAB!) — the allusion to The Treasure of the Sierra Madre has been removed, in deference to being...
