Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to...
An IIR 'DC Removal' Filter
It seems to me that DC removal filters (also called "DC blocking filters") have been of some moderate interest recently on the dsprelated.com Forum web page. With that notion in mind I thought I'd post a little information, from Chapter 13 of my "Understanding DSP" book, regarding infinite impulse response (IIR) DC removal filters.
Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA
The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt. The project overview was discussed in the previous blog...
Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction
Last time, we talked about error correction and detection, covering some basics like Hamming distance, CRCs, and Hamming codes. If you are new to this topic, I would strongly suggest going back to read that article before this one. This time we...
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an...
Two Easy Ways To Test Multistage CIC Decimation Filters
This article presents two very easy ways to test the performance of multistage cascaded integrator-comb (CIC) decimation filters. Anyone implementing CIC filters should take note of the following proposed CIC filter test methods.
ADC Clock Jitter Model, Part 2 – Random Jitter
In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered...
ADC Clock Jitter Model, Part 1 – Deterministic Jitter
Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold...
FFT Interpolation Based on FFT Samples: A Detective Story With a Surprise Ending
This blog presents several interesting things I recently learned regarding the estimation of a spectral value located at a frequency lying between previously computed FFT spectral samples. My curiosity about this FFT interpolation process was triggered by reading a spectrum analysis paper written by three astronomers.
Phase or Frequency Shifter Using a Hilbert Transformer
In this article, we'll describe how to use a Hilbert transformer to make a phase shifter or frequency shifter. In either case, the input is a real signal and the output is a real signal. We'll use some simple Matlab code to simulate these systems. After that, we'll go into a little more detail on Hilbert transformer theory and design.
DSP Jobs Soaring | Ready Your Interview Skills
Digital Signal Processing (DSP) technology is the cornerstone of most cutting edge technology today. For example, digital signal processing drives much of machine learning in artificial intelligence (AI). It also steers eyesight and movement...
A DSP Quiz Question
Here's a DSP Quiz Question that I hope you find mildly interestingBACKGROUNDDue to the periodic natures an N-point discrete Fourier transform (DFT) sequence and that sequence’s inverse DFT, it is occasionally reasonable to graphically plot...
Setting Carrier to Noise Ratio in Simulations
When simulating digital receivers, we often want to check performance with added Gaussian noise. In this article, I’ll derive the simple equations for the rms noise level needed to produce a desired carrier to noise ratio (CNR or...
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an...
Update to a Narrow Bandpass Filter in Octave or Matlab
Following my earlier blog post (June 2020) featuring a Narrow Bandpass Filter, I’ve had some useful feedback and suggestions. This has inspired me to come up with an updated version, incorporating the following changes compared to the earlier...
An Efficient Full-Band Sliding DFT Spectrum Analyzer
In this blog I present two computationally efficient full-band discrete Fourier transform (DFT) networks that compute the 0th bin and all the positive-frequency bin outputs for an N-point DFT in real-time on a sample-by-sample basis. An Even-N...
Add a Power Marker to a Power Spectral Density (PSD) Plot
Perhaps we should call most Power Spectral Density (PSD) calculations relative PSD, because usually we don’t have to worry about absolute power levels. However, for cases (e.g., measurements or simulations) where we are concerned with...
Understanding and Preventing Overflow (I Had Too Much to Add Last Night)
Happy Thanksgiving! Maybe the memory of eating too much turkey is fresh in your mind. If so, this would be a good time to talk about overflow. In the world of floating-point arithmetic, overflow is possible but not particularly common. You can...
Stereophonic Amplitude-Panning: A Derivation of the "Tangent Law"
This article presents a derivation of the "Tangent Law"
An IIR 'DC Removal' Filter
It seems to me that DC removal filters (also called "DC blocking filters") have been of some moderate interest recently on the dsprelated.com Forum web page. With that notion in mind I thought I'd post a little information, from Chapter 13 of my "Understanding DSP" book, regarding infinite impulse response (IIR) DC removal filters.
