ITS- > Hi, I have a question about TMS320DM642 EMIF related ibis simulation. > Previously I designed a DSP board with TMS320C6713 and all of...

ITS- > Hi, I have a question about TMS320DM642 EMIF related ibis simulation. > Previously I designed a DSP board with TMS320C6713 and all of its > simulations with SDRAM went perfectly ok. > > However when I performed the ibis simulation for a newer board, using > TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some > non-monotonic rise and fall waveform over the data p

Hi, I have a question about TMS320DM642 EMIF related ibis simulation. Previously I designed a DSP board with TMS320C6713 and all of its...

Hi, I have a question about TMS320DM642 EMIF related ibis simulation. Previously I designed a DSP board with TMS320C6713 and all of its simulations with SDRAM went perfectly ok. However when I performed the ibis simulation for a newer board, using TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some non-monotonic rise and fall waveform over the data pins (AED00 for example)...

Hello, I am trying to use an already existing DSP BIOS project built for C67xx and migrate it to be usable in C64xx. In the C67xx...

Hello, I am trying to use an already existing DSP BIOS project built for C67xx and migrate it to be usable in C64xx. In the C67xx project there is SDRAM configuration present under the EMIF settings. In case of C64xx there is EMIFA and EMIFB. I want to be able to delete the SDRAM configuration from under EMIF settings and add new configurations under

Hi, We are using a DM641 based custom board. We are using M29W160EB NOR Flash in the CE1 space of DM641 EMIF-A. We studied the Flash...

Hi, We are using a DM641 based custom board. We are using M29W160EB NOR Flash in the CE1 space of DM641 EMIF-A. We studied the Flash datasheet and developed a device driver to read and write from / to Flash device. The Flash chip has a Ready/Busy pin which can be connected to the ARDY pin of DM641 EMIF. When we program the Flash, the Flash chip pulls the DM641 EMIF ARDY pin low indic...

please help me.... I like to get the test vector about EMIF external FIFO interface.... XOE,XRE,XWE,XCEx.... ...

please help me.... I like to get the test vector about EMIF external FIFO interface.... XOE,XRE,XWE,XCEx....

I wonder that when I modify the value of emif register value like CExCTL, what changes occur in DSP chip. Roughly, I know that the...

I wonder that when I modify the value of emif register value like CExCTL, what changes occur in DSP chip. Roughly, I know that the CExCTL is related to RD, WR, or CE signal. But, I want to know exact information about it. Please, explain about it.

Hi, we're running into big troubles with this errata. I increased the EMIF clock to more than half of the core clock but this...

Hi, we're running into big troubles with this errata. I increased the EMIF clock to more than half of the core clock but this seems not to help. It only decreases the probability of the error. Is there any other workaround for this problem? Another possibility would be to have

Hi All Can anyone please correct me if I'm wrong, but if I write ce2[0x5]=0x31; with int *ce2 =(int *) (0xA0000000); to emif on...

Hi All Can anyone please correct me if I'm wrong, but if I write ce2[0x5]=0x31; with int *ce2 =(int *) (0xA0000000); to emif on 6711DSK then on the address lines I must see the following: EA2 = 3.3V (1) EA3 = 0V (0) EA4 = 3.3V (1) and ED0

Hello, I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA. In order to do that I need to know the *IO functionalites of the DSK....

Hello, I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA. In order to do that I need to know the *IO functionalites of the DSK. * **Can anyone kindly suggest any manuals or documents to go about before programming the EMIF on the DSK. Programming examples will be of great help to me. Do I also need to learn about GPIO ?? Thanks, -- Varun

Hi all ... Can someone please explain the following ... I am reading inputs from 3 ADC's (resolution 12, 10 and 10 ...

Hi all ... Can someone please explain the following ... I am reading inputs from 3 ADC's (resolution 12, 10 and 10 respectively) on ED[0..31] of 6711 dsk... howz the data flow in this case ? does GBCNTRL register of EMIF aid me in reading this data ? i plan

Hello please can any one guide me regarding CE of EMIF i have done all the setting regarding CE2 or CE3. and then i am using EDMA to transfer...

Hello please can any one guide me regarding CE of EMIF i have done all the setting regarding CE2 or CE3. and then i am using EDMA to transfer the data from DDR2 to CE3 but i cant write anything on that CE3 area. I have tried all the relevent seting using CSL library but no use.I am writing the code i used to configue EMID and EMDA please i need urgent help . in main i called these two functi...

i am using 6 bit phase shifter which has to be interface with the dsp kit tms320c6455. which port i have to use? can i use emif? how to send a...

i am using 6 bit phase shifter which has to be interface with the dsp kit tms320c6455. which port i have to use? can i use emif? how to send a control bits to the phase shifter? which port address i ahve to use here? _____________________________________

Hi, I'm building a simple circuit featuring a 6211 and 16Mb of Micron SDRAM (32-wide) that I hope to mass produce as cheaply as...

Hi, I'm building a simple circuit featuring a 6211 and 16Mb of Micron SDRAM (32-wide) that I hope to mass produce as cheaply as possible. Studying the Spectrum Digital designs, they series terminate all the EMIF signals with 33 ohm resistor networks. - Is t

Hi I noticed that for the C6713/3B DSP there is an internal configurable PLL to generate various clock speeds for DSP core...

Hi I noticed that for the C6713/3B DSP there is an internal configurable PLL to generate various clock speeds for DSP core as well as peripherals. Knowing that, is it of any advantage to route the CLKOUT2/CLKOUT3 pins to ECLKIN of EMIF instead of using the int

TM, On 6/25/08, TM wrote: > > Hi > I have a DM642 one with 720 Mhz and another with 500 Mhz. For both of them > the SDRAM is same,...

TM, On 6/25/08, TM wrote: > > Hi > I have a DM642 one with 720 Mhz and another with 500 Mhz. For both of them > the SDRAM is same, but the one for 720 Mhz DM642 runs 133 mHz speed and > other at 100 Mhz. IS there any changes needed for the gel file where we > initialize the EMIF. If yes please do tell me what could be the > configuration for the same. They should be

Dear Williams, Thank U very very much for help, I guess your right but hat about Rulph Chassing's book (C6713+C6416 & APPLICATIONS) that...

Dear Williams, Thank U very very much for help, I guess your right but hat about Rulph Chassing's book (C6713+C6416 & APPLICATIONS) that e disccussed about that before. This bokk has a EMIF project for 32 LED (FFTradix2), and I made a PCB for that exact hardware, but I couldn't complete the program (as u told me before,these projects on chassing's book are incomplete). Ho can I make those LE...

Hello Everyone, I am trying to do a Peripheral Device Transfer ( a PDT write by programming the EDMA and EMIFA registers ) from a FIFO on a...

Hello Everyone, I am trying to do a Peripheral Device Transfer ( a PDT write by programming the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a DSK6416 SDRAM. My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope it DOES NOT look like a square wave but rather like a sinusoidal wave with a frequency of 125 MHz and amplitude is 1.6 V. Isn't ECLKOUT su...

Hi, all. In reference design for C6416 provided from TI, the SDRAM (supporting 167MHz) clock frequency is 150 MHz. However, the maximum...

Hi, all. In reference design for C6416 provided from TI, the SDRAM (supporting 167MHz) clock frequency is 150 MHz. However, the maximum EMIF frequency is 133 MHz in the datasheet of TMS320C6416 (@720MHz,7E). How is it possible?

hello !     i have some trouble with C6203 EMIF.     the value in the EMIF registers is: ...

hello !     i have some trouble with C6203 EMIF.     the value in the EMIF registers is: (this is according to my board condition)

Hi H.Mahdavi I have exactly the same problem Can you please help me (If you have the solution)? PF > > > > >...

Hi H.Mahdavi I have exactly the same problem Can you please help me (If you have the solution)? PF > > > > > Hello Dear, > We use C6416 DSP processor(DSK C6416 @720MHz) and Dughter card include FPGA chip (Virtex-E). > we want to read data from FPGA around 60 MBytes/Sec trough EMIF port of DSP Processor. but we can't do it. > we examine asynchroun and synchron meth