## Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Developing and Validating Simulation ModelsThis article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

- Part 1: Introduction
- Part 2: Ideal Model Examples
- Part 3: Sampled Data Aspects
- Part 4: Engineering of Evaluation Hardware
- Part 5:

## Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

Introduction to the topicThis is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

- Part 1:

## Dealing With Fixed Point Fractions

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...

## Constrained Integer Behavior

The wheels go round and round, round and round ...Integer arithmetic is ubiquitous in digital hardware implementations, it's prolific in the control and data-paths. When using fixed width (constrained) integers, overflow and underflow is business as usual.

Building with IntegersThe subtitle of this post mentions a wheel - before I get to the wheel I want to look at an example. The recursive-windowed-averager (rwa, a.k.a moving average)...

## Spline interpolation

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

IntroductionSplines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...

## Signed serial-/parallel multiplication

Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm

Summary- A detailed discussion of bit-level trickstery in signed-signed multiplication
- Algorithm based on Wikipedia example
- Includes a Verilog implementation with parametrized bit width

A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...

## Python scipy.signal IIR Filtering: An Example

IntroductionIn the last posts I reviewed how to use the Python scipy.signal package to design digital infinite impulse response (IIR) filters, specifically, using the iirdesign function (IIR design I and IIR design II ). In this post I am going to conclude the IIR filter design review with an example.

Previous posts:

## A Fixed-Point Introduction by Example

IntroductionThe finite-word representation of fractional numbers is known as fixed-point. Fixed-point is an interpretation of a 2's compliment number usually signed but not limited to sign representation. It extends our finite-word length from a finite set of integers to a finite set of rational real numbers [1]. A fixed-point representation of a number consists of integer and fractional components. The bit length is defined...

## DSP Algorithm Implementation: A Comprehensive Approach

As DSP engineers, ultimately we are required to design and implement specific DSP algorithms. The first step is to make a choice on which algorithm to use, e.g. for filtering should we use FIR or IIR. Then we can go a little bit deeper into the, high level, implementation details, e.g. use the symmetry in FIR filter to reduce complexity. When the algorithm is clear, the first step is to test and simulate the algorithm in a high level language like MATLAB.

After we reach confidence in...

## Half-band filter on Xilinx FPGA

1. DSP48 Slice in Xilinx FPGAThere are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending on the device, but broadly similar.

Figure 1: A whole DSP48A1 Slice in Spartan6 (www.xilinx.com)

2. Symmetric Systolic Half-band FIRFigure 2: Symmetric Systolic Half-band FIR Filter

3. Two-channel Symmetric Systolic Half-band FIRFigure 3: 2-Channel...

## Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...

## Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

Some Design and Simulation Considerations for Sampled-Data ControllersThis article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.

- Part 1: Introduction

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## DSP Algorithm Implementation: A Comprehensive Approach

As DSP engineers, ultimately we are required to design and implement specific DSP algorithms. The first step is to make a choice on which algorithm to use, e.g. for filtering should we use FIR or IIR. Then we can go a little bit deeper into the, high level, implementation details, e.g. use the symmetry in FIR filter to reduce complexity. When the algorithm is clear, the first step is to test and simulate the algorithm in a high level language like MATLAB.

After we reach confidence in...

## Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:

## Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

Introduction to the topicThis is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

- Part 1:

## Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...

## Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.

Additional design...## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Developing and Validating Simulation ModelsThis article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

- Part 1: Introduction
- Part 2: Ideal Model Examples
- Part 3: Sampled Data Aspects
- Part 4: Engineering of Evaluation Hardware
- Part 5:

## DSP Algorithm Implementation: A Comprehensive Approach

As DSP engineers, ultimately we are required to design and implement specific DSP algorithms. The first step is to make a choice on which algorithm to use, e.g. for filtering should we use FIR or IIR. Then we can go a little bit deeper into the, high level, implementation details, e.g. use the symmetry in FIR filter to reduce complexity. When the algorithm is clear, the first step is to test and simulate the algorithm in a high level language like MATLAB.

After we reach confidence in...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Developing and Validating Simulation ModelsThis article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

- Part 1: Introduction
- Part 2: Ideal Model Examples
- Part 3: Sampled Data Aspects
- Part 4: Engineering of Evaluation Hardware
- Part 5:

## Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...

## Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

Some Design and Simulation Considerations for Sampled-Data ControllersThis article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.

- Part 1: Introduction

## Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.

Additional design...## Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...

## Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:

## Constrained Integer Behavior

The wheels go round and round, round and round ...Integer arithmetic is ubiquitous in digital hardware implementations, it's prolific in the control and data-paths. When using fixed width (constrained) integers, overflow and underflow is business as usual.

Building with IntegersThe subtitle of this post mentions a wheel - before I get to the wheel I want to look at an example. The recursive-windowed-averager (rwa, a.k.a moving average)...