Two Bin Exact Frequency Formulas for a Pure Real Tone in a DFT
Introduction
This is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT) by deriving exact formulas for the frequency of a real tone in a DFT. This time it is a two bin version. The approach taken is a vector based one similar to the approach used in "Three Bin Exact Frequency Formulas for a Pure Complex Tone in a DFT"[1]. The real valued formula presented in this article actually preceded, and was the basis for the complex three bin...
Errata for the book: 'Understanding Digital Signal Processing'
Errata 3rd Ed. International Version.pdfErrata 3rd Ed. International Version.pdf
This blog post provides, in one place, the errata for each of the many different Editions/Printings of my book Understanding Digital Signal Processing.
If you would like the errata for your copy of the book, merely scroll down and click on the appropriate red line below. For the American versions of the various Editions of the book you'll need to know the "Printing Number" of your copy of the...
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
Some Design and Simulation Considerations for Sampled-Data Controllers
This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.
- Part 1: Introduction
Finally got a drone!
As a reader of my blog, you already know that I have been making videos lately and thoroughly enjoying the process. When I was in Germany early this summer (and went 280 km/h in a porsche!) to produce SEGGER's 25th anniversary video, the company bought a drone so we could get an aerial shot of the party (at about the 1:35 mark in this video). Since then, I have been obsessing on buying a drone for myself and finally made the move a few weeks ago - I acquired a used DJI...
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
Developing and Validating Simulation ModelsThis article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.
- Part 1: Introduction
- Part 2: Ideal Model Examples
- Part 3: Sampled Data Aspects
- Part 4: Engineering of Evaluation Hardware
- Part 5:
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
Introduction to the topicThis is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.
- Part 1:
Exact Near Instantaneous Frequency Formulas Best at Zero Crossings
IntroductionThis is an article that is the last of my digression from trying to give a better understanding of the Discrete Fourier Transform (DFT). It is along the lines of the last two.
In those articles, I presented exact formulas for calculating the frequency of a pure tone signal as instantaneously as possible in the time domain. Although the formulas work for both real and complex signals (something that does not happen with frequency domain formulas), for real signals they...
SEGGER's 25th Anniversary Video
Chances are you will find this video more interesting to watch if you take five minutes to first read the story of the week I spent at SEGGER's headquarters at the end of June.
The video is only a little more than 2 minutes long. If you decide to watch it, make sure to go full screen and I would really love to read your thoughts about it in the comments down bellow. Do you think a video like this succeeds in making the viewer want to learn more about the company?...
Above-Average Smoothing of Impulsive Noise
In this blog I show a neat noise reduction scheme that has the high-frequency noise reduction behavior of a traditional moving average process but with much better impulsive-noise suppression.
In practice we may be required to make precise measurements in the presence of highly-impulsive noise. Without some sort of analog signal conditioning, or digital signal processing, it can be difficult to obtain stable and repeatable, measurements. This impulsive-noise smoothing trick,...
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
Noise shaping
eywords: Quantization noise; noise shaping
A brief introduction to noise shaping, with firm resolve not to miss the forest for the trees. We may still stumble over some assorted roots. Matlab example code is included.
QuantizationFig. 1 shows a digital signal that is reduced to a lower bit width, for example a 16 bit signal being sent to a 12 bit digital-to-analog converter. Rounding to the nearest output value is obviously the best that can be done to minimize the error of each...
Resolving 'Can't initialize target CPU' on TI C6000 DSPs - Part 2
Configuration
The previous article discussed CCS configuration. The prerequisite for the following discussion is a valid CCS configuration file. All references will be for CCS 3.3, but they may be used or adapted to other versions of CCS. From the previous discussion, we know that the configuration file is located at 'C:\CCStudio_v3.3\cc\bin\brddat\ccBrd0.dat'.
XDS510 Emulators
Initial discussion will address only XDS510 class emulators that support TI drivers and utilities. This will...
Design IIR Band-Reject Filters
In this post, I show how to design IIR Butterworth band-reject filters, and provide two Matlab functions for band-reject filter synthesis. Earlier posts covered IIR Butterworth lowpass [1] and bandpass [2] filters. Here, the function br_synth1.m designs band-reject filters based on null frequency and upper -3 dB frequency, while br_synth2.m designs them based on lower and upper -3 dB frequencies. I’ll discuss the differences between the two approaches later in this...
Computing the Group Delay of a Filter
I just learned a new method (new to me at least) for computing the group delay of digital filters. In the event this process turns out to be interesting to my readers, this blog describes the method. Let's start with a bit of algebra so that you'll know I'm not making all of this up.
Assume we have the N-sample h(n) impulse response of a digital filter, with n being our time-domain index, and that we represent the filter's discrete-time Fourier transform (DTFT), H(ω), in polar form...
Coupled-Form 2nd-Order IIR Resonators: A Contradiction Resolved
This blog clarifies how to obtain and interpret the z-domain transfer function of the coupled-form 2nd-order IIR resonator. The coupled-form 2nd-order IIR resonator was developed to overcome a shortcoming in the standard 2nd-order IIR resonator. With that thought in mind, let's take a brief look at a standard 2nd-order IIR resonator.
Standard 2nd-Order IIR Resonator A block diagram of the standard 2nd-order IIR resonator is shown in Figure 1(a). You've probably seen that block diagram many...
Find Aliased ADC or DAC Harmonics (with animation)
When a sinewave is applied to a data converter (ADC or DAC), device nonlinearities produce harmonics. If a harmonic frequency is greater than the Nyquist frequency, the harmonic appears as an alias. In this case, it is not at once obvious if a given spur is a harmonic, and if so, its order. In this article, we’ll present Matlab code to simulate the data converter nonlinearities and find the harmonic alias frequencies. Note that Analog Devices has an online tool for...
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...
Third-Order Distortion of a Digitally-Modulated Signal
Analog designers are always harping about amplifier third-order distortion. Why? In this article, we’ll look at why third-order distortion is important, and simulate a QAM signal with third-order distortion.
In the following analysis, we assume that signal phase at the amplifier output is not a function of amplitude. With this assumption, the output y of a non-ideal amplifier can be written as a power series of the input signal x:
$$y=...
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:
"I noticed that you didn't discuss z-plane regions of convergence here. In my undergraduate DSP class we spent a lot of classroom and homework time on the ...
Complex Down-Conversion Amplitude Loss
This blog illustrates the signal amplitude loss inherent in a traditional complex down-conversion system. (In the literature of signal processing, complex down-conversion is also called "quadrature demodulation.")
The general idea behind complex down-conversion is shown in Figure 1(a). And the traditional hardware block diagram of a complex down-converter is shown in Figure 1(b).
Let's assume the input to our down-conversion system is an analog radio frequency (RF) signal,...
DFT Graphical Interpretation: Centroids of Weighted Roots of Unity
IntroductionThis is an article to hopefully give a better understanding to the Discrete Fourier Transform (DFT) by framing it in a graphical interpretation. The bin calculation formula is shown to be the equivalent of finding the center of mass, or centroid, of a set of points. Various examples are graphed to illustrate the well known properties of DFT bin values. This treatment will only consider real valued signals. Complex valued signals can be analyzed in a similar manner with...
A New Contender in the Digital Differentiator Race
This blog proposes a novel differentiator worth your consideration. Although simple, the differentiator provides a fairly wide 'frequency range of linear operation' and can be implemented, if need be, without performing numerical multiplications.
BackgroundIn reference [1] I presented a computationally-efficient tapped-delay line digital differentiator whose $h_{ref}(k)$ impulse response is:
$$ h_{ref}(k) = {-1/16}, \ 0, \ 1, \ 0, \ {-1}, \ 0, \ 1/16 \tag{1} $$and...
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...
Linear Feedback Shift Registers for the Uninitiated, Part XIV: Gold Codes
Last time we looked at some techniques using LFSR output for system identification, making use of the peculiar autocorrelation properties of pseudorandom bit sequences (PRBS) derived from an LFSR.
This time we’re going to jump back to the field of communications, to look at an invention called Gold codes and why a single maximum-length PRBS isn’t enough to save the world using spread-spectrum technology. We have to cover two little side discussions before we can get into Gold...
Embedded World 2018 - The Interviews
Once again this year, I had the chance to go to Embedded World in Nuremberg Germany. And once again this year, I brought my video equipment to try and capture some of the most interesting things at the show.
Something new this year, I asked Jacob Beningo if he would partner with me in doing interviews with a few vendors. I would operate the camera while Jacob would ask the right questions to the vendors to make them talk about the key products/features that...
ADC Clock Jitter Model, Part 1 – Deterministic Jitter
Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2]. As shown in Figure 1, the ADC has a sample/hold function that is clocked by a sample clock. Jitter on the sample clock causes the sampling instants to vary from the ideal sample time. This transfers the jitter from the sample clock to the input signal.
In this article, I present a Matlab...
Launch of Youtube Channel: My First Videos - Embedded World 2017
I went to Embedded World 2017 in Nuremberg with an ambitious plan; I would make video highlights of several exhibits (booths) to be presented to the *Related sites audience. I would try to make the vendors focus their pitch on the essential in order to produce a one to three minutes video per booth.
So far my experience with making videos was limited to family videos, so I knew I had lots of reading to do and lots of Youtube videos and tutorials to watch. Trade shows are...
Two Easy Ways To Test Multistage CIC Decimation Filters
This blog presents two very easy ways to test the performance of multistage cascaded integrator-comb (CIC) decimation filters [1]. Anyone implementing CIC filters should take note of the following proposed CIC filter test methods.
Introduction
Figure 1 presents a multistage decimate by D CIC filter where the number of stages is S = 3. The '↓D' operation represents downsampling by integer D (discard all but every Dth sample), n is the input time index, and m is the output time index.
Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction
Last time, we talked about Gold codes, a specially-constructed set of pseudorandom bit sequences (PRBS) with low mutual cross-correlation, which are used in many spread-spectrum communications systems, including the Global Positioning System.
This time we are wading into the field of error detection and correction, in particular CRCs and Hamming codes.
Ernie, You Have a Banana in Your EarI have had a really really tough time writing this article. I like the...
A Recipe for a Common Logarithm Table
IntroductionThis is an article that is a digression from trying to give a better understanding to the Discrete Fourier Transform (DFT).
A method for building a table of Base 10 Logarithms, also known as Common Logarithms, is featured using math that can be done with paper and pencil. The reader is assumed to have some familiarity with logarithm functions. This material has no dependency on the material in my previous blog articles.
If you were ever curious about how...
