Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA
By week 5 the project delivered parameterized MyHDL implementations of multiple digital filter topologies and started integration with PyFDA. The post walks through a behavioral direct-form I FIR, cascaded second-order-section implementations for FIR and IIR using structural modeling, and a parallel IIR design that concatenates per-section outputs for final summation. All designs infer order and coefficients from PyFDA, with examples in the filter-blocks repository.
Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction
Jason Sachs demystifies Reed-Solomon codes with hands-on examples and pragmatic tips for embedded engineers. The article shows why RS encoding is just polynomial division in GF(2^m), why decoding is mathematically heavier, and how to implement encoders in Python and in C-friendly form using LFSRs and table-driven methods. Read this for working code, generator-polynomial examples, and an embedded-minded view of RS practicalities.
Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction
CRCs and Hamming codes look a lot less magical when you view them as redundancy with a purpose. Jason Sachs walks from parity bits and checksums into finite-field polynomial arithmetic, then shows how CRCs map cleanly onto LFSRs and how Hamming codes use syndromes to locate single-bit errors. It is a practical tour of error detection and correction, with enough worked examples to make the theory feel usable.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
Stephane Boucher is heading to Sensors Expo in San Jose for the first time, and he is bringing cameras to capture demos and build a highlights video. He is also looking for roommates for a roomy Airbnb near the convention center, plus local tips for making the most of a free day in the Bay Area. If you are attending, there is also a registration discount code and a VIP pass giveaway in the mix.
Digital PLL's, Part 3 -- Phase Lock an NCO to an External Clock
Phase-locking a numerically controlled oscillator to an external clock that is unrelated to system clocks is practical and largely unexplored. Neil Robertson presents a time-domain digital PLL that converts the ADC-sampled clock into I/Q with a Hilbert transformer and measures phase error with a compact complex phase detector. The post shows loop-filter coefficient formulas and simulations that reveal how ADC quantization and Gaussian clock noise map into NCO phase noise and how loop bandwidth shapes the result.
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Sriyash Caculo is building a bridge between filter design and hardware by implementing digital filter blocks in MyHDL and integrating them with PyFDA as part of a Google Summer of Code project. The work aims to convert PyFDA floating point designs into fixed point MyHDL blocks that automatically generate VHDL or Verilog, with tests and tutorials to ensure correctness and usability.
Two Easy Ways To Test Multistage CIC Decimation Filters
Rick Lyons shows that you can validate multistage CIC decimation filters with just two obvious tests, no elaborate spectral setup required. Apply a unit-sample impulse to check a combinatorial yout(1) value when D ≥ S, or feed an all-ones step to confirm an S-sample transient followed by a DS steady state; the Appendix ties both checks to Pascal's triangle and binomial math.
ADC Clock Jitter Model, Part 2 – Random Jitter
Neil Robertson shows how to simulate ADC sample-clock random jitter in Matlab, moving from band-limited Gaussian noise to wideband and close-in phase noise. The post highlights practical artifacts such as aliasing of wideband clock noise, the 20*log10 dependence of jitter sidebands on input frequency, and why cubic interpolation plus a custom noise_filter produces accurate rms and spectral results engineers can trust.
Take Control of Noise with Spectral Averaging
Spectral averaging turns noisy FFT outputs into repeatable, measurable spectra by trading time for noise control. This post explains the practical difference between RMS averaging, which reduces variance without changing the noise floor, and vector averaging, which can lower the noise floor but requires phase-coherent, triggered inputs. It also shows how linear and exponential weighting affect reaction time for live displays and measurement accuracy.
Linear Feedback Shift Registers for the Uninitiated, Part XIV: Gold Codes
Gold codes solve a practical spread-spectrum problem, sharing one PRBS across many transmitters eventually runs into ugly synchronization and correlation issues. Jason Sachs walks through why shifted copies of a single LFSR sequence are not enough, then shows how preferred pairs of m-sequences create a family of Gold codes with bounded cross-correlation. The post wraps with Python experiments and a UART DSSS demo that decodes multiple overlapping messages cleanly.
Weighted least-squares FIR with shared coefficients
Markus Nentwig demonstrates how to design FIR filters that share coefficients across delay taps, allowing multiplier reuse and reduced implementation cost. He reimplements Lawson's iterative reweighted least-squares for complex-valued FIRs and provides Matlab/Octave code you can adapt for nonstandard constraints. The post explains iteration weight logic, the Toeplitz special-case with Levinson-Durbin, and practical trade-offs between multiplier count and stopband performance.
The Most Interesting FIR Filter Equation in the World: Why FIR Filters Can Be Linear Phase
Rick Lyons pulls back the curtain on a little-known coefficient constraint that makes complex-coefficient FIR filters exhibit linear phase. Rather than simple symmetry of real coefficients, the key is a conjugate-reflection relation involving the filter phase at DC, which collapses to ordinary symmetry for real taps. The post includes derivations, intuition using the inverse DTFT, and a Matlab example to verify the result.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Accurate Measurement of a Sinusoid's Peak Amplitude Based on FFT Data
Measuring a sinewave's peak from FFT data can be severely biased by scalloping loss, producing errors up to 36.3 percent. Rick Lyons demonstrates how to apply a flat-top window via frequency-domain convolution to the FFT bins, cutting maximum amplitude error to about 0.02 dB compared with 3.9 dB for rectangular windows. The post includes Matlab code and practical caveats for reliable use.
How Discrete Signal Interpolation Improves D/A Conversion
Digital interpolation can drastically simplify the analog filtering that follows a DAC, lowering cost and improving output quality. Rick Lyons explains how inserting zeros and applying a digital lowpass filter (interpolation-by-two) raises the effective sample rate, reduces the DAC sin(x)/x droop, and widens the analog filter transition band. The post gives practical intuition and spectral illustrations engineers can reuse in real designs.
Do you like the new Comments System?
Stephane Boucher has just rolled out a new comments system for the DSPRelated blogs and wants feedback from readers. He’s asking the community to try it out, share thoughts, and help shake out any issues before it gets expanded to the code snippets and papers sections.
Python scipy.signal IIR Filtering: An Example
Christopher Felton walks through using scipy.signal IIR filters to demodulate PWM signals, using spectrum and spectrogram analysis to show what works and what does not. He demonstrates using filtfilt to avoid phase delay, compares a single narrow IIR to a very high order FIR, and shows how staged IIR filtering and multirate ideas give much better attenuation. Includes an FPGA-ready MyHDL PWM model.
ADC Clock Jitter Model, Part 2 – Random Jitter
Neil Robertson shows how to simulate ADC sample-clock random jitter in Matlab, moving from band-limited Gaussian noise to wideband and close-in phase noise. The post highlights practical artifacts such as aliasing of wideband clock noise, the 20*log10 dependence of jitter sidebands on input frequency, and why cubic interpolation plus a custom noise_filter produces accurate rms and spectral results engineers can trust.
A Simplified Matlab Function for Power Spectral Density
Neil Robertson provides a tiny Matlab wrapper around pwelch that simplifies PSD computation by preselecting a Kaiser window, default overlap, and converting units from W/Hz to dBW/bin. Call psd_simple(x,nfft,fs) to get PdB and a frequency vector, with nfft controlling whether DFT averaging is used. The post includes examples showing the effect of averaging and explains the Kaiser window processing loss.
Computing Chebyshev Window Sequences
Rick Lyons gives a compact, practical recipe for building M-sample Chebyshev (Dolph) windows with user-set sidelobe levels, not just theory. The post walks through computing α and A(m), evaluating the Nth-degree Chebyshev polynomial, doing an inverse DFT, and the simple postprocessing needed to form a symmetric time-domain window. A worked 9-sample example and an implementation caveat for even-length windows make this immediately usable.
Compute Modulation Error Ratio (MER) for QAM
Neil Robertson shows how to define and compute Modulation Error Ratio (MER) for QAM using a simplified baseband model and decision-slice errors. The post derives per-symbol and averaged MER formulas, explains when MER tracks carrier-to-noise ratio under AWGN and matched root-Nyquist filters, and provides example Pav values for QAM-16 and QAM-64 plus a Matlab script and practical tips.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Instantaneous Frequency Measurement
Measuring carrier frequency quickly and with minimal data matters in radar and signal characterization. Parth Vakil explains the delay-and-multiply instantaneous frequency measurement technique, shows how analytic signals and multiple delays resolve the 2π ambiguity, and demonstrates noise, phase-wrapping, and interferer effects using MATLAB code. He also outlines practical mitigations like phase unwrapping and channelization.
The DFT of Finite-Length Time-Reversed Sequences
Rick Lyons digs into a surprisingly under-documented corner of DSP, showing how finite-length time reversal changes a sequence's DFT. The post distinguishes flip and circular time-reversal, gives closed-form DFT relationships, and explains why modulo N arithmetic matters. Engineers get ready-to-use tables and derivations that clarify when and how time reversal affects spectral analysis.
Linear Feedback Shift Registers for the Uninitiated, Part XIV: Gold Codes
Gold codes solve a practical spread-spectrum problem, sharing one PRBS across many transmitters eventually runs into ugly synchronization and correlation issues. Jason Sachs walks through why shifted copies of a single LFSR sequence are not enough, then shows how preferred pairs of m-sequences create a family of Gold codes with bounded cross-correlation. The post wraps with Python experiments and a UART DSSS demo that decodes multiple overlapping messages cleanly.
Time-Domain Periodicity and the Discrete Fourier Transform
Finite-length observation windows change how tones appear in a DFT, and Eric Jacobsen shows how the convolution theorem explains the familiar sin(x)/x main lobe and sidelobes. He contrasts two consistent viewpoints: viewing the DFT as a windowed signal convolved with the window transform, or as the transform of a periodically repeated sequence. Practical tips on zero-padding, bin spacing, and phase effects help avoid common misinterpretations.
Design study: 1:64 interpolating pulse shaping FIR
Markus Nentwig presents a practical 1:64 root-raised cosine interpolator built from cascaded FIR stages that slashes computational cost. By separating pulse shaping from rate conversion, designing each interpolator to suppress only known alias bands, and equalizing the pulse shape, the design achieves just 4.69 MACs per output, roughly 12 percent of a straight polyphase implementation while meeting EVM targets.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction
CRCs and Hamming codes look a lot less magical when you view them as redundancy with a purpose. Jason Sachs walks from parity bits and checksums into finite-field polynomial arithmetic, then shows how CRCs map cleanly onto LFSRs and how Hamming codes use syndromes to locate single-bit errors. It is a practical tour of error detection and correction, with enough worked examples to make the theory feel usable.
ADC Clock Jitter Model, Part 1 -- Deterministic Jitter
Clock jitter on ADC sample clocks corrupts high-frequency signals, and this post builds a practical MATLAB model to show exactly how deterministic (periodic) jitter maps into phase modulation and discrete sidebands. The author explains a parabolic-interpolation approach using twice-rate samples, demonstrates examples from single tones to pulses, and matches simulation spectra to closed-form sideband formulas so engineers can predict jitter effects.
