## 5G NR QC-LDPC Encoding Algorithm

3GPP 5G has been focused on structured LDPC codes known as quasi-cyclic low-density parity-check (QC-LDPC) codes, which exhibit advantages over other types of LDPC codes with respect to the hardware implementations of encoding and decoding using simple shift registers and logic circuits.

5G NR QC-LDPC  Circulant Permutation Matrix

A circular permutation matrix ${\bf I}(P_{i,j})$ of size $Z_c \times Z_c$ is obtained by circularly shifting the identity matrix $\bf I$ of...

## Interpolation Basics

This article covers interpolation basics, and provides a numerical example of interpolation of a time signal.  Figure 1 illustrates what we mean by interpolation.  The top plot shows a continuous time signal, and the middle plot shows a sampled version with sample time Ts.  The goal of interpolation is to increase the sample rate such that the new (interpolated) sample values are close to the values of the continuous signal at the sample times [1].  For example, if...

## A Two Bin Solution

July 12, 2019
Introduction

This is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT) by showing an implementation of how the parameters of a real pure tone can be calculated from just two DFT bin values. The equations from previous articles are used in tandem to first calculate the frequency, and then calculate the amplitude and phase of the tone. The approach works best when the tone is between the two DFT bins in terms of frequency.

The Coding...

## Reduced-Delay IIR Filters

This blog gives the results of a preliminary investigation of reduced-delay (reduced group delay) IIR filters based on my understanding of the concepts presented in a recent interesting blog by Steve Maslen [1].

Development of a Reduced-Delay 2nd-Order IIR Filter

Maslen's development of a reduced-delay 2nd-order IIR filter begins with a traditional prototype filter, HTrad, shown in Figure 1(a). The first modification to the prototype filter is to extract the b0 feedforward coefficient...

## Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.

Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

## A Direct Digital Synthesizer with Arbitrary Modulus

Suppose you have a system with a 10 MHz sample clock, and you want to generate a sampled sinewave at any frequency below 5 MHz on 500 kHz spacing; i.e., 0.5, 1.0, 1.5, … MHz.  In other words, f = k*fs/20, where k is an integer and fs is sample frequency.  This article shows how to do this using a simple Direct Digital Synthesizer (DDS) with a look-up table that is at most 20 entries long.   We’ll also demonstrate a Quadrature-output DDS.  A note on...

## Somewhat Off Topic: Deciphering Transistor Terminology

I recently learned something mildly interesting about transistors, so I thought I'd share my new knowledge with you folks. Figure 1 shows a p-n-p transistor comprising a small block of n-type semiconductor sandwiched between two blocks of p-type semiconductor.

The terminology of "emitter" and "collector" seems appropriate, but did you ever wonder why the semiconductor block in the center is called the "base"? The word base seems inappropriate because the definition of the word base is:...

## Reducing IIR Filter Computational Workload

This blog describes a straightforward method to significantly reduce the number of necessary multiplies per input sample of traditional IIR lowpass and highpass digital filters.

Reducing IIR Filter Computations Using Dual-Path Allpass Filters

We can improve the computational speed of a lowpass or highpass IIR filter by converting that filter into a dual-path filter consisting of allpass filters as shown in Figure 1.

...

## A Lesson In Engineering Humility

Let's assume you were given the task to design and build the 12-channel telephone transmission system shown in Figure 1.

Figure 1

At a rate of 8000 samples/second, each telephone's audio signal is sampled and converted to a 7-bit binary sequence of pulses. The analog signals at Figure 1's nodes A, B, and C are presented in Figure 2.

Figure 2

I'm convinced that some of you subscribers to this dsprelated.com web site could accomplish such a design & build task....

In an earlier post [1], we implemented lowpass IIR filters using a cascade of second-order IIR filters, or biquads.

This post provides a Matlab function to do the same for Butterworth bandpass IIR filters.  Compared to conventional implementations, bandpass filters based on biquads are less sensitive to coefficient quantization [2].  This becomes important when designing narrowband filters.

A biquad section block diagram using the Direct Form II structure [3,4] is...

## Peak to Average Power Ratio and CCDF

Peak to Average Power Ratio (PAPR) is often used to characterize digitally modulated signals.  One example application is setting the level of the signal in a digital modulator.  Knowing PAPR allows setting the average power to a level that is just low enough to minimize clipping.

However, for a random signal, PAPR is a statistical quantity.  We have to ask, what is the probability of a given peak power?  Then we can decide where to set the average...

Introduction

Many DSP problems have close ties with the analog world. For example, a switched-mode audio power amplifier uses a digital control loop to open and close power transistors driving an analog filter. There are commercial tools for digital-analog cosimulation: Simulink comes to mind, and mainstream EDA vendors support VHDL-AMS or Verilog-A in their...

## Padé Delay is Okay Today

This article is going to be somewhat different in that I’m not really writing it for the typical embedded systems engineer. Rather it’s kind of a specialized topic, so don’t be surprised if you get bored and move on to something else. That’s fine by me.

Anyway, let’s just jump ahead to the punchline. Here’s a numerical simulation of a step response to a $p=126, q=130$ Padé approximation of a time delay:

Impressed? Maybe you should be. This...

## Phase and Amplitude Calculation for a Pure Real Tone in a DFT: Method 1

May 21, 20151 comment
Introduction

This is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT) by deriving exact formulas for the phase and amplitude of a non-integer frequency real tone in a DFT. The linearity of the Fourier Transform is exploited to reframe the problem as the equivalent of finding a set of coordinates in a specific vector space. The found coordinates are then used to calculate the phase and amplitude of the pure real tone in the DFT. This article...

## Free Goodies from Embedded World - What to Do Next?

I told you I would go on a hunt for free stuff at Embedded World in order to build a bundle for someone to win.

## A Simplified Matlab Function for Power Spectral Density

In an earlier post [1], I showed how to compute power spectral density (PSD) of a discrete-time signal using the Matlab function pwelch [2].  Pwelch is a useful function because it gives the correct output, and it has the option to average multiple Discrete Fourier Transforms (DFTs).  However, a typical function call has five arguments, and it can be hard to remember how to set them all and how they default.

In this post, I create a simplified PSD function by putting a...

## TCP/IP interface (Matlab/Octave)

Communicate with measurement instruments via Ethernet (no-toolbox-Matlab or Octave)

Purpose

Measurement automation is digital signal processing in a wider sense: Getting a digital signal from an analog world usually involves some measurement instruments, for example a spectrum analyzer. Modern instruments, and also many off-the-shelf prototyping boards such as FPGA cards [1] or microcontrollers [2] are able to communicate via Ethernet. Here, I provide some basic mex-functions (compiled C...

## Digital PLL's -- Part 2

In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter.  Now let’s look at this PLL in the Z-domain [1, 2].  We will find that the response is characterized by a loop natural frequency ωn and damping coefficient ζ.

Having a Z-domain model of the DPLL will allow us to do three things:

Compute the values of loop filter proportional gain KL and integrator gain KI that give the desired loop natural...