## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

Additional...

## Polar Coding Notes: A Simple Proof

For any B-DMC $W$, the channels $\{W_N^{(i)}\}$ polarize in the sense that, for any fixed $\delta \in (0, 1)$, as $N$ goes to infinity through powers of two, the fraction of indices $i \in \{1, \dots, N\}$ for which $I(W_N^{(i)}) \in (1 − \delta, 1]$ goes to $I(W)$ and the fraction for which $I(W_N^{(i)}) \in [0, \delta)$ goes to $1−I(W)^{[1]}$.

Mrs. Gerber’s Lemma

Mrs. Gerber’s Lemma provides a lower bound on the entropy of the modulo-$2$ sum of two binary random...

## Polar Coding Notes: Channel Combining and Channel Splitting

Channel Combining

Channel combining is a step that combines copies of a given B-DMC $W$ in a recursive manner to produce a vector channel $W_N : {\cal X}^N \to {\cal Y}^N$, where $N$ can be any power of two, $N=2^n, n\le0^{[1]}$.

The notation $u_1^N$ as shorthand for denoting a row vector $(u_1, \dots , u_N)$.

The vector channel $W_N$ is the virtual channel between the input sequence $u_1^N$ to a linear encoder and the output sequence $y^N_1$ of $N$...

## Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.

Project overviewThe project “Digital Filter Blocks in MyHDL and PyFDA integration" aims...

## Sensors Expo - Trip Report & My Best Video Yet!

This was my first time at Sensors Expo and my second time in Silicon Valley and I must say I had a great time.

Before I share with you what I find to be, by far, my best 'highlights' video yet for a conference/trade show, let me try to entertain you with a few anecdotes from this trip. If you are not interested by my stories or maybe don't have the extra minutes needed to read them, please feel free to skip to the end of this blog post to watch the...

## Design a DAC sinx/x Corrector

This post provides a Matlab function that designs linear-phase FIR sinx/x correctors. It includes a table of fixed-point sinx/x corrector coefficients for different DAC frequency ranges.

A sinx/x corrector is a digital (or analog) filter used to compensate for the sinx/x roll-off inherent in the digital to analog conversion process. In DSP math, we treat the digital signal applied to the DAC is a sequence of impulses. These are converted by the DAC into contiguous pulses...

## Off Topic: Refraction in a Varying Medium

IntroductionThis article is another digression from a better understanding of the DFT. In fact, it is a digression from DSP altogether. However, since many of the readers here are Electrical Engineers and other folks who are very scientifically minded, I hope this article is of interest. A differential vector equation is derived for the trajectory of a point particle in a field of varying index of refraction. This applies to light, of course, but since it is a purely theoretical...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA

This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks.

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...

## Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA

This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.

This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.

Direct form-I FIR filterThe equation specifies the direct form I...

## Why Time-Domain Zero Stuffing Produces Multiple Frequency-Domain Spectral Images

This blog explains why, in the process of time-domain interpolation (sample rate increase), zero stuffing a time sequence with zero-valued samples produces an increased-length time sequence whose spectrum contains replications of the original time sequence's spectrum.

Background

The traditional way to interpolate (sample rate increase) an x(n) time domain sequence is shown in Figure 1.

Figure 1

The '↑ L' operation in Figure 1 means to...

## Polyphase filter / Farrows interpolation

Hello,

this article is meant to give a quick overview over polyphase filtering and Farrows interpolation.

A good reference with more depth is for example Fred Harris' paper: http://www.signumconcepts.com/IP_center/paper018.pdf

The task is as follows: Interpolate a band-limited discrete-time signal at a variable offset between samples.In other words:Delay the signal by a given amount with sub-sample accuracy.Both mean the same.

The picture below shows samples (black) representing...

## DFT Graphical Interpretation: Centroids of Weighted Roots of Unity

IntroductionThis is an article to hopefully give a better understanding to the Discrete Fourier Transform (DFT) by framing it in a graphical interpretation. The bin calculation formula is shown to be the equivalent of finding the center of mass, or centroid, of a set of points. Various examples are graphed to illustrate the well known properties of DFT bin values. This treatment will only consider real valued signals. Complex valued signals can be analyzed in a similar manner with...

## Pulse Shaping in Single-Carrier Communication Systems

Some common conceptual hurdles for beginning communications engineers have to do with "Pulse Shaping" or the closely-related, even synonymous, topics of "matched filtering", "Nyquist filtering", "Nyquist pulse", "pulse filtering", "spectral shaping", etc. Some of the confusion comes from the use of terms like "matched filter" which has a broader meaning in the more general field of signal processing or detection theory. Likewise "Raised Cosine" has a different meaning or application in this...

## Setting the 3-dB Cutoff Frequency of an Exponential Averager

This blog discusses two ways to determine an exponential averager's weighting factor so that the averager has a given 3-dB cutoff frequency. Here we assume the reader is familiar with exponential averaging lowpass filters, also called a "leaky integrators", to reduce noise fluctuations that contaminate constant-amplitude signal measurements. Exponential averagers are useful because they allow us to implement lowpass filtering at a low computational workload per output sample.

Figure 1 shows...

## ADC Clock Jitter Model, Part 2 – Random Jitter

In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered Gaussian sequence as the jitter source. What we are calling jitter can also be called time jitter, phase jitter, or phase noise. It’s all the same phenomenon. Typically, we call it jitter when we have a time-domain representation,...

## Compute Modulation Error Ratio (MER) for QAM

This post defines the Modulation Error Ratio (MER) for QAM signals, and shows how to compute it. As we’ll see, in the absence of impairments other than noise, the MER tracks the signal’s Carrier-to-Noise Ratio (over a limited range). A Matlab script at the end of the PDF version of this post computes MER for a simplified QAM-64 system.

Figure 1 is a simplified block diagram of a QAM system. The transmitter includes a source of QAM symbols, a root-Nyquist...

## Simple Discrete-Time Modeling of Lossy LC Filters

There are many software applications that allow modeling LC filters in the frequency domain. But sometimes it is useful to have a time domain model, such as when you need to analyze a mixed analog and DSP system. For example, the system in Figure 1 includes an LC filter as well as a DSP portion. The LC filter could be an anti-alias filter, a channel filter, or some other LC network. For a design using undersampling, the filter would be bandpass [1]. By modeling...

## Signal Processing Contest in Python (PREVIEW): The Worst Encoder in the World

When I posted an article on estimating velocity from a position encoder, I got a number of responses. A few of them were of the form "Well, it's an interesting article, but at slow speeds why can't you just take the time between the encoder edges, and then...." My point was that there are lots of people out there which take this approach, and don't take into account that the time between encoder edges varies due to manufacturing errors in the encoder. For some reason this is a hard concept...

## Exponential Smoothing with a Wrinkle

IntroductionThis is an article to hopefully give a better understanding to the Discrete Fourier Transform (DFT) by providing a set of preprocessing filters to improve the resolution of the DFT. Because of the exponential nature of sinusoidal functions, they have special mathematical properties when exponential smoothing is applied to them. These properties are derived and explained in this blog article.

Basic Exponential Smoothing

Exponential smoothing is also known as...

## Shared-multiplier polyphase FIR filter

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

IntroductionA polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...

## Design of an anti-aliasing filter for a DAC

Overview- Octaveforge / Matlab design script. Download: here
- weighted numerical optimization of Laplace-domain transfer function
- linear-phase design, optimizes vector error (magnitude and phase)
- design process calculates and corrects group delay internally
- includes sinc() response of the sample-and-hold stage in the ADC
- optionally includes multiplierless FIR filter

Digital-to-analog conversion connects digital...

## Discrete Wavelet Transform Filter Bank Implementation (part 1)

UPDATE: Added graphs and code to explain the frequency division of the branches

The focus of this article is to briefly explain an implementation of this transform and several filter bank forms. Theoretical information about DWT can be found elsewhere.

First of all, a 'quick and dirty' simplified explanation of the differences between DFT and DWT:

The DWT (Discrete Wavelet Transform), simply put, is an operation that receives a signal as an input (a vector of data) and...

## Instantaneous Frequency Measurement

I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. But, of course, with simplicity, there come drawbacks (sometimes...especially with this one!).

In the world of Radar detection and characterization, one of the key characteristics of interest is the carrier frequency of the signal. If the radar is pulsed, you will have a very wide bandwidth, a...

## Recruiting New Bloggers!

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,

## An Astounding Digital Filter Design Application

I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.

What I Liked About the ASN Filter DesignerWith typical filter design software packages the user enters numerical values for the...

## Spline interpolation

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

IntroductionSplines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...

## Should DSP Undergraduate Students Study z-Transform Regions of Convergence?

Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:

"I noticed that you didn't discuss z-plane regions of convergence here. In my undergraduate DSP class we spent a lot of classroom and homework time on the ...

## Correcting an Important Goertzel Filter Misconception

Recently I was on the Signal Processing Stack Exchange web site (a question and answer site for DSP people) and I read a posted question regarding Goertzel filters [1]. One of the subscribers posted a reply to the question by pointing interested readers to a Wikipedia web page discussing Goertzel filters [2]. I noticed the Wiki web site stated that a Goertzel filter:

"...is marginally stable and vulnerable tonumerical error accumulation when computed usinglow-precision arithmetic and...