Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.
Fig 1. Making a Transmission Line, with the Circuit Emulator
Additional...
Polar Coding Notes: A Simple Proof
For any B-DMC $W$, the channels $\{W_N^{(i)}\}$ polarize in the sense that, for any fixed $\delta \in (0, 1)$, as $N$ goes to infinity through powers of two, the fraction of indices $i \in \{1, \dots, N\}$ for which $I(W_N^{(i)}) \in (1 − \delta, 1]$ goes to $I(W)$ and the fraction for which $I(W_N^{(i)}) \in [0, \delta)$ goes to $1−I(W)^{[1]}$.
Mrs. Gerber’s Lemma
Mrs. Gerber’s Lemma provides a lower bound on the entropy of the modulo-$2$ sum of two binary random...
Polar Coding Notes: Channel Combining and Channel Splitting
Channel Combining
Channel combining is a step that combines copies of a given B-DMC $W$ in a recursive manner to produce a vector channel $W_N : {\cal X}^N \to {\cal Y}^N$, where $N$ can be any power of two, $N=2^n, n\le0^{[1]}$.
The notation $u_1^N$ as shorthand for denoting a row vector $(u_1, \dots , u_N)$.
The vector channel $W_N$ is the virtual channel between the input sequence $u_1^N$ to a linear encoder and the output sequence $y^N_1$ of $N$...
Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA
The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.
The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.
Project overviewThe project “Digital Filter Blocks in MyHDL and PyFDA integration" aims...
Sensors Expo - Trip Report & My Best Video Yet!
This was my first time at Sensors Expo and my second time in Silicon Valley and I must say I had a great time.
Before I share with you what I find to be, by far, my best 'highlights' video yet for a conference/trade show, let me try to entertain you with a few anecdotes from this trip. If you are not interested by my stories or maybe don't have the extra minutes needed to read them, please feel free to skip to the end of this blog post to watch the...
Design a DAC sinx/x Corrector
This post provides a Matlab function that designs linear-phase FIR sinx/x correctors. It includes a table of fixed-point sinx/x corrector coefficients for different DAC frequency ranges.
A sinx/x corrector is a digital (or analog) filter used to compensate for the sinx/x roll-off inherent in the digital to analog conversion process. In DSP math, we treat the digital signal applied to the DAC is a sequence of impulses. These are converted by the DAC into contiguous pulses...
Off Topic: Refraction in a Varying Medium
IntroductionThis article is another digression from a better understanding of the DFT. In fact, it is a digression from DSP altogether. However, since many of the readers here are Electrical Engineers and other folks who are very scientifically minded, I hope this article is of interest. A differential vector equation is derived for the trajectory of a point particle in a field of varying index of refraction. This applies to light, of course, but since it is a purely theoretical...
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.
Fig 1. The evaluation platform
Additional design...
Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks.
So, why do we need to integrate and how do we go about it?
As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...
Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.
This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.
Direct form-I FIR filterThe equation specifies the direct form I...
The DSP Online Conference - Right Around the Corner!
It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..
It all started with a post in the DSPRelated forum about three months ago. We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community. So my goal with the post in the forum was to see if...
Free Goodies from Embedded World - What to Do Next?
I told you I would go on a hunt for free stuff at Embedded World in order to build a bundle for someone to win.
A Simpler Goertzel Algorithm
In this blog I propose a Goertzel algorithm that is simpler than the version of the Goertzel algorithm that is traditionally presented DSP textbooks. Below I very briefly describe the DSP textbook version of the Goertzel algorithm followed by a description of my proposed simpler algorithm.
The Traditional DSP Textbook Goertzel Algorithm
The so-called Goertzel algorithm is used to efficiently compute a single mth-bin sample of an N-point discrete Fourier transform (DFT) [1-4]. The...
Modeling Anti-Alias Filters
Digitizing a signal using an Analog to Digital Converter (ADC) usually requires an anti-alias filter, as shown in Figure 1a. In this post, we’ll develop models of lowpass Butterworth and Chebyshev anti-alias filters, and compute the time domain and frequency domain output of the ADC for an example input signal. We’ll also model aliasing of Gaussian noise. I hope the examples make the textbook explanations of aliasing seem a little more real. Of course, modeling of...
Noise shaping
eywords: Quantization noise; noise shaping
A brief introduction to noise shaping, with firm resolve not to miss the forest for the trees. We may still stumble over some assorted roots. Matlab example code is included.
QuantizationFig. 1 shows a digital signal that is reduced to a lower bit width, for example a 16 bit signal being sent to a 12 bit digital-to-analog converter. Rounding to the nearest output value is obviously the best that can be done to minimize the error of each...
Discrete-Time PLLs, Part 1: Basics
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Wavelets II - Vanishing Moments and Spectral Factorization
In the previous blog post I described the workings of the Fast Wavelet Transform (FWT) and how wavelets and filters are related. As promised, in this article we will see how to construct useful filters. Concretely, we will find a way to calculate the Daubechies filters, named after Ingrid Daubechies, who invented them and also laid much of the mathematical foundations for wavelet analysis.
Besides the content of the last post, you should be familiar with basic complex algebra, the...
A Fast Real-Time Trapezoidal Rule Integrator
This blog presents a computationally-efficient network for computing real‑time discrete integration using the Trapezoidal Rule.
Background
While studying what is called "N-sample Romberg integration" I noticed that such an integration process requires the computation of many individual smaller‑sized integrations using the Trapezoidal Rule integration method [1]. My goal was to create a computationally‑fast real‑time Trapezoidal Rule integration network to increase the processing...
Discrete Wavelet Transform Filter Bank Implementation (part 1)
UPDATE: Added graphs and code to explain the frequency division of the branches
The focus of this article is to briefly explain an implementation of this transform and several filter bank forms. Theoretical information about DWT can be found elsewhere.
First of all, a 'quick and dirty' simplified explanation of the differences between DFT and DWT:
The DWT (Discrete Wavelet Transform), simply put, is an operation that receives a signal as an input (a vector of data) and...
A Fast Guaranteed-Stable Sliding DFT Algorithm
This blog presents a most computationally-efficient guaranteed-stable real-time sliding discrete Fourier transform (SDFT) algorithm. The phrase “real-time” means the network computes one spectral output sample, equal to a single-bin output of an N‑point discrete Fourier transform (DFT), for each input signal sample.
Proposed Guaranteed Stable SDFT
My proposed guaranteed stable SDFT, whose development is given in [1], is shown in Figure 1(a). The output sequence Xk(n) is an N-point...
Design of an anti-aliasing filter for a DAC
Overview- Octaveforge / Matlab design script. Download: here
- weighted numerical optimization of Laplace-domain transfer function
- linear-phase design, optimizes vector error (magnitude and phase)
- design process calculates and corrects group delay internally
- includes sinc() response of the sample-and-hold stage in the ADC
- optionally includes multiplierless FIR filter
Digital-to-analog conversion connects digital...
Sampling bandpass signals
Sampling bandpass signals 1.1 IntroductionIt is known [1], [3] that bandpass signals can be sampled with a sampling frequency which is lower than the sampling frequency according to the sampling theorem.
Fig. 1 shows an example of how the spectrum of a bandpass signal sampled with $f_s$ (Fig. 1a) arises in the baseband with $−f_s / 2 ≤ f < f_s/2$. The bandpass signal is assumed to have a center frequency $f_c = (f_{max} + f_{min})/2$ and bandwidth $\Delta f...
Discrete Wavelet Transform Filter Bank Implementation (part 1)
UPDATE: Added graphs and code to explain the frequency division of the branches
The focus of this article is to briefly explain an implementation of this transform and several filter bank forms. Theoretical information about DWT can be found elsewhere.
First of all, a 'quick and dirty' simplified explanation of the differences between DFT and DWT:
The DWT (Discrete Wavelet Transform), simply put, is an operation that receives a signal as an input (a vector of data) and...
Instantaneous Frequency Measurement
I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. But, of course, with simplicity, there come drawbacks (sometimes...especially with this one!).
In the world of Radar detection and characterization, one of the key characteristics of interest is the carrier frequency of the signal. If the radar is pulsed, you will have a very wide bandwidth, a...
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Spline interpolation
A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog
IntroductionSplines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:
"I noticed that you didn't discuss z-plane regions of convergence here. In my undergraduate DSP class we spent a lot of classroom and homework time on the ...
An Astounding Digital Filter Design Application
I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.
What I Liked About the ASN Filter DesignerWith typical filter design software packages the user enters numerical values for the...
Correcting an Important Goertzel Filter Misconception
Recently I was on the Signal Processing Stack Exchange web site (a question and answer site for DSP people) and I read a posted question regarding Goertzel filters [1]. One of the subscribers posted a reply to the question by pointing interested readers to a Wikipedia web page discussing Goertzel filters [2]. I noticed the Wiki web site stated that a Goertzel filter:
"...is marginally stable and vulnerable tonumerical error accumulation when computed usinglow-precision arithmetic and...Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...