## Evaluate Window Functions for the Discrete Fourier Transform

The Discrete Fourier Transform (DFT) operates on a finite length time sequence to compute its spectrum. For a continuous signal like a sinewave, you need to capture a segment of the signal in order to perform the DFT. Usually, you also need to apply a window function to the captured signal before taking the DFT [1 - 3]. There are many different window functions and each produces a different approximation of the spectrum. In this post, we’ll present Matlab code that...

## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

Additional...

## Polar Coding Notes: A Simple Proof

For any B-DMC $W$, the channels $\{W_N^{(i)}\}$ polarize in the sense that, for any fixed $\delta \in (0, 1)$, as $N$ goes to infinity through powers of two, the fraction of indices $i \in \{1, \dots, N\}$ for which $I(W_N^{(i)}) \in (1 − \delta, 1]$ goes to $I(W)$ and the fraction for which $I(W_N^{(i)}) \in [0, \delta)$ goes to $1−I(W)^{[1]}$.

Mrs. Gerber’s Lemma

Mrs. Gerber’s Lemma provides a lower bound on the entropy of the modulo-$2$ sum of two binary random...

## Polar Coding Notes: Channel Combining and Channel Splitting

Channel Combining

Channel combining is a step that combines copies of a given B-DMC $W$ in a recursive manner to produce a vector channel $W_N : {\cal X}^N \to {\cal Y}^N$, where $N$ can be any power of two, $N=2^n, n\le0^{[1]}$.

The notation $u_1^N$ as shorthand for denoting a row vector $(u_1, \dots , u_N)$.

The vector channel $W_N$ is the virtual channel between the input sequence $u_1^N$ to a linear encoder and the output sequence $y^N_1$ of $N$...

## Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.

Project overviewThe project “Digital Filter Blocks in MyHDL and PyFDA integration" aims...

## Sensors Expo - Trip Report & My Best Video Yet!

This was my first time at Sensors Expo and my second time in Silicon Valley and I must say I had a great time.

Before I share with you what I find to be, by far, my best 'highlights' video yet for a conference/trade show, let me try to entertain you with a few anecdotes from this trip. If you are not interested by my stories or maybe don't have the extra minutes needed to read them, please feel free to skip to the end of this blog post to watch the...

## Design a DAC sinx/x Corrector

This post provides a Matlab function that designs linear-phase FIR sinx/x correctors. It includes a table of fixed-point sinx/x corrector coefficients for different DAC frequency ranges.

A sinx/x corrector is a digital (or analog) filter used to compensate for the sinx/x roll-off inherent in the digital to analog conversion process. In DSP math, we treat the digital signal applied to the DAC is a sequence of impulses. These are converted by the DAC into contiguous pulses...

## Off Topic: Refraction in a Varying Medium

IntroductionThis article is another digression from a better understanding of the DFT. In fact, it is a digression from DSP altogether. However, since many of the readers here are Electrical Engineers and other folks who are very scientifically minded, I hope this article is of interest. A differential vector equation is derived for the trajectory of a point particle in a field of varying index of refraction. This applies to light, of course, but since it is a purely theoretical...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA

This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks.

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...

## Free DSP Books on the Internet

While surfing the "net" I have occasionally encountered signal processing books whose chapters could be downloaded to my computer. I started keeping a list of those books and, over the years, that list has grown to over forty books. Perhaps the list will be of interest to you.

Please know, all of the listed books are copyrighted. The copyright holders have graciously provided their books free of charge for downloading for individual use, but multiple copies must not be made or printed. As...

## Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!

Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.

## The Number 9, Not So Magic After All

This blog is not about signal processing. Rather, it discusses an interesting topic in number theory, the magic of the number 9. As such, this blog is for people who are charmed by the behavior and properties of numbers.

For decades I've thought the number 9 had tricky, almost magical, qualities. Many people feel the same way. I have a book on number theory, whose chapter 8 is titled "Digits — and the Magic of 9", that discusses all sorts of interesting mathematical characteristics of the...

## Generating Complex Baseband and Analytic Bandpass Signals

There are so many different time- and frequency-domain methods for generating complex baseband and analytic bandpass signals that I had trouble keeping those techniques straight in my mind. Thus, for my own benefit, I created a kind of reference table showing those methods. I present that table for your viewing pleasure in this blog.

For clarity, I define a complex baseband signal as follows: derived from an input analog xbp(t)bandpass signal whose spectrum is shown in Figure 1(a), or...

## Padé Delay is Okay Today

This article is going to be somewhat different in that I’m not really writing it for the typical embedded systems engineer. Rather it’s kind of a specialized topic, so don’t be surprised if you get bored and move on to something else. That’s fine by me.

Anyway, let’s just jump ahead to the punchline. Here’s a numerical simulation of a step response to a \( p=126, q=130 \) Padé approximation of a time delay:

Impressed? Maybe you should be. This...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

Additional design...

## Signed serial-/parallel multiplication

Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm

Summary- A detailed discussion of bit-level trickstery in signed-signed multiplication
- Algorithm based on Wikipedia example
- Includes a Verilog implementation with parametrized bit width

A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...

## Plotting Discrete-Time Signals

A discrete-time sinusoid can have frequency up to just shy of half the sample frequency. But if you try to plot the sinusoid, the result is not always recognizable. For example, if you plot a 9 Hz sinusoid sampled at 100 Hz, you get the result shown in the top of Figure 1, which looks like a sine. But if you plot a 35 Hz sinusoid sampled at 100 Hz, you get the bottom graph, which does not look like a sine when you connect the dots. We typically want the plot of a...

## How to Find a Fast Floating-Point atan2 Approximation

Context Over a short period of time, I came across nearly identical approximations of the two parameter arctangent function, atan2, developed by different companies, in different countries, and even in different decades. Fascinated with how the coefficients used in these approximations were derived, I set out to find them. This atan2 implementation is based around a rational approximation of arctangent on the domain -1 to 1:$$ atan(z) \approx \dfrac{z}{1.0 +...

## Why Time-Domain Zero Stuffing Produces Multiple Frequency-Domain Spectral Images

This blog explains why, in the process of time-domain interpolation (sample rate increase), zero stuffing a time sequence with zero-valued samples produces an increased-length time sequence whose spectrum contains replications of the original time sequence's spectrum.

Background

The traditional way to interpolate (sample rate increase) an x(n) time domain sequence is shown in Figure 1.

Figure 1

The '↑ L' operation in Figure 1 means to...

## Design of an anti-aliasing filter for a DAC

Overview- Octaveforge / Matlab design script. Download: here
- weighted numerical optimization of Laplace-domain transfer function
- linear-phase design, optimizes vector error (magnitude and phase)
- design process calculates and corrects group delay internally
- includes sinc() response of the sample-and-hold stage in the ADC
- optionally includes multiplierless FIR filter

Digital-to-analog conversion connects digital...

## Recruiting New Bloggers!

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,

## Discrete Wavelet Transform Filter Bank Implementation (part 1)

UPDATE: Added graphs and code to explain the frequency division of the branches

The focus of this article is to briefly explain an implementation of this transform and several filter bank forms. Theoretical information about DWT can be found elsewhere.

First of all, a 'quick and dirty' simplified explanation of the differences between DFT and DWT:

The DWT (Discrete Wavelet Transform), simply put, is an operation that receives a signal as an input (a vector of data) and...

## An Astounding Digital Filter Design Application

I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.

What I Liked About the ASN Filter DesignerWith typical filter design software packages the user enters numerical values for the...

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...

## Spline interpolation

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

IntroductionSplines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...

## Dealing With Fixed Point Fractions

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...

## Instantaneous Frequency Measurement

I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. But, of course, with simplicity, there come drawbacks (sometimes...especially with this one!).

In the world of Radar detection and characterization, one of the key characteristics of interest is the carrier frequency of the signal. If the radar is pulsed, you will have a very wide bandwidth, a...

## Should DSP Undergraduate Students Study z-Transform Regions of Convergence?

Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:

"I noticed that you didn't discuss z-plane regions of convergence here. In my undergraduate DSP class we spent a lot of classroom and homework time on the ...