## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

November 22, 2018

This article will look at a design approach for feedback controllers featuring  low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

## Polar Coding Notes: A Simple Proof

November 8, 2018

For any B-DMC $W$, the channels $\{W_N^{(i)}\}$ polarize in the sense that, for any fixed $\delta \in (0, 1)$, as $N$ goes to infinity through powers of two, the fraction of indices $i \in \{1, \dots, N\}$ for which $I(W_N^{(i)}) \in (1 − \delta, 1]$ goes to $I(W)$ and the fraction for which $I(W_N^{(i)}) \in [0, \delta)$ goes to $1−I(W)^{[1]}$.

Mrs. Gerber’s Lemma

Mrs. Gerber’s Lemma provides a lower bound on the entropy of the modulo-$2$ sum of two binary random...

## Polar Coding Notes: Channel Combining and Channel Splitting

October 19, 2018

Channel Combining

Channel combining is a step that combines copies of a given B-DMC $W$ in a recursive manner to produce a vector channel $W_N : {\cal X}^N \to {\cal Y}^N$, where $N$ can be any power of two, $N=2^n, n\le0^{[1]}$.

The notation $u_1^N$ as shorthand for denoting a row vector $(u_1, \dots , u_N)$.

The vector channel $W_N$ is the virtual channel between the input sequence $u_1^N$ to a linear encoder and the output sequence $y^N_1$ of $N$...

## Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

August 13, 20181 comment

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.

Project overview

The project “Digital Filter Blocks in MyHDL and PyFDA integration" aims...

## Sensors Expo - Trip Report & My Best Video Yet!

This was my first time at Sensors Expo and my second time in Silicon Valley and I must say I had a great time.

Before I share with you what I find to be, by far, my best 'highlights' video yet for a conference/trade show, let me try to entertain you with a few anecdotes from this trip.  If you are not interested by my stories or maybe don't have the extra minutes needed to read them, please feel free to skip to the end of this blog post to watch the...

## Design a DAC sinx/x Corrector

This post provides a Matlab function that designs linear-phase FIR sinx/x correctors.  It includes a table of fixed-point sinx/x corrector coefficients for different DAC frequency ranges.

A sinx/x corrector is a digital (or analog) filter used to compensate for the sinx/x roll-off inherent in the digital to analog conversion process.  In DSP math, we treat the digital signal applied to the DAC is a sequence of impulses.  These are converted by the DAC into contiguous pulses...

## Off Topic: Refraction in a Varying Medium

July 11, 20181 comment
Introduction

This article is another digression from a better understanding of the DFT. In fact, it is a digression from DSP altogether. However, since many of the readers here are Electrical Engineers and other folks who are very scientifically minded, I hope this article is of interest. A differential vector equation is derived for the trajectory of a point particle in a field of varying index of refraction. This applies to light, of course, but since it is a purely theoretical...

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

July 9, 2018

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

## Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA

July 9, 2018

This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks.

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...

## Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA

June 22, 2018

This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.

• Implementation of filter blocks in MyHDL
• Design of interface between filter blocks and PyFDA

This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.

Direct form-I FIR filter

The equation specifies the direct form I...

## Shared-multiplier polyphase FIR filter

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

Introduction

A polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...

## Design of an anti-aliasing filter for a DAC

August 18, 2012
Overview
• weighted numerical optimization of Laplace-domain transfer function
• linear-phase design, optimizes vector error (magnitude and phase)
• design process calculates and corrects group delay internally
• includes sinc() response of the sample-and-hold stage in the ADC
• optionally includes multiplierless FIR filter
Problem Figure 1: Typical FIR-DAC-analog lowpass line-up

Digital-to-analog conversion connects digital...

## Discrete Wavelet Transform Filter Bank Implementation (part 1)

October 27, 20101 comment

UPDATE: Added graphs and code to explain the frequency division of the branches

First of all, a 'quick and dirty' simplified explanation of the differences between DFT and DWT:

The DWT (Discrete Wavelet Transform), simply put, is an operation that receives a signal as an input (a vector of data) and...

## Instantaneous Frequency Measurement

I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. But, of course, with simplicity, there come drawbacks (sometimes...especially with this one!).

In the world of Radar detection and characterization, one of the key characteristics of interest is the carrier frequency of the signal. If the radar is pulsed, you will have a very wide bandwidth, a...

## Recruiting New Bloggers!

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick LyonsJason Sachs, Victor Yurkovsky, Mike Silva, Markus NentwigGene BrenimanStephen Friederichs,

## An Astounding Digital Filter Design Application

I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.

What I Liked About the ASN Filter Designer

With typical filter design software packages the user enters numerical values for the...

## Spline interpolation

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA.  This situation is shown in Figure 1.  Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2.  This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1].  In that PLL, we...