## Interpolation Basics

This article covers interpolation basics, and provides a numerical example of interpolation of a time signal. Figure 1 illustrates what we mean by interpolation. The top plot shows a continuous time signal, and the middle plot shows a sampled version with sample time Ts. The goal of interpolation is to increase the sample rate such that the new (interpolated) sample values are close to the values of the continuous signal at the sample times [1]. For example, if...

## A Two Bin Solution

IntroductionThis is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT) by showing an implementation of how the parameters of a real pure tone can be calculated from just two DFT bin values. The equations from previous articles are used in tandem to first calculate the frequency, and then calculate the amplitude and phase of the tone. The approach works best when the tone is between the two DFT bins in terms of frequency.

The Coding...## Reduced-Delay IIR Filters

This blog gives the results of a preliminary investigation of reduced-delay (reduced group delay) IIR filters based on my understanding of the concepts presented in a recent interesting blog by Steve Maslen [1].

Development of a Reduced-Delay 2nd-Order IIR Filter

Maslen's development of a reduced-delay 2nd-order IIR filter begins with a traditional prototype filter, HTrad, shown in Figure 1(a). The first modification to the prototype filter is to extract the b0 feedforward coefficient...

## Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

## A Direct Digital Synthesizer with Arbitrary Modulus

Suppose you have a system with a 10 MHz sample clock, and you want to generate a sampled sinewave at any frequency below 5 MHz on 500 kHz spacing; i.e., 0.5, 1.0, 1.5, … MHz. In other words, f = k*fs/20, where k is an integer and fs is sample frequency. This article shows how to do this using a simple Direct Digital Synthesizer (DDS) with a look-up table that is at most 20 entries long. We’ll also demonstrate a Quadrature-output DDS. A note on...

## Somewhat Off Topic: Deciphering Transistor Terminology

I recently learned something mildly interesting about transistors, so I thought I'd share my new knowledge with you folks. Figure 1 shows a p-n-p transistor comprising a small block of n-type semiconductor sandwiched between two blocks of p-type semiconductor.

The terminology of "emitter" and "collector" seems appropriate, but did you ever wonder why the semiconductor block in the center is called the "base"? The word base seems inappropriate because the definition of the word base is:...

## Reducing IIR Filter Computational Workload

This blog describes a straightforward method to significantly reduce the number of necessary multiplies per input sample of traditional IIR lowpass and highpass digital filters.

Reducing IIR Filter Computations Using Dual-Path Allpass Filters

We can improve the computational speed of a lowpass or highpass IIR filter by converting that filter into a dual-path filter consisting of allpass filters as shown in Figure 1.

...## A Lesson In Engineering Humility

Let's assume you were given the task to design and build the 12-channel telephone transmission system shown in Figure 1.

Figure 1

At a rate of 8000 samples/second, each telephone's audio signal is sampled and converted to a 7-bit binary sequence of pulses. The analog signals at Figure 1's nodes A, B, and C are presented in Figure 2.

Figure 2

I'm convinced that some of you subscribers to this dsprelated.com web site could accomplish such a design & build task....## IIR Bandpass Filters Using Cascaded Biquads

In an earlier post [1], we implemented lowpass IIR filters using a cascade of second-order IIR filters, or biquads.

This post provides a Matlab function to do the same for Butterworth bandpass IIR filters. Compared to conventional implementations, bandpass filters based on biquads are less sensitive to coefficient quantization [2]. This becomes important when designing narrowband filters.

A biquad section block diagram using the Direct Form II structure [3,4] is...

## Controlling a DSP Network's Gain: A Note For DSP Beginners

This blog briefly discusses a topic well-known to experienced DSP practitioners but may not be so well-known to DSP beginners. The topic is the proper way to control a digital network's gain. Digital Network Gain Control Figure 1 shows a collection of networks I've seen, in the literature of DSP, where strict gain control is implemented.

FIGURE 1. Examples of digital networks whose initial operations are input signal...

## Live Streaming from Embedded World!

For those of you who won't be attending Embedded World this year, I will try to be your eyes and ears by video streaming live from the show floor.

I am not talking improvised streaming from a phone, but real, high quality HD streaming with a high-end camera and a device that will bond three internet connections (one wifi and two cellular) to ensure a steady, and hopefully reliable, stream. All this to hopefully give those of you who cannot be there in person a virtual...

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...

## Ancient History

The other day I was downloading an IDE for a new (to me) OS. When I went to compile some sample code, it failed. I went onto a forum, where I was told "if you read the release notes you'd know that the peripheral libraries are in a legacy download". Well damn! Looking back at my previous versions I realized I must have done that and forgotten about it. Everything changes, and keeping up with it takes time and effort.

When I first started with microprocessors we...

## The DFT Magnitude of a Real-valued Cosine Sequence

This blog may seem a bit trivial to some readers here but, then again, it might be of some value to DSP beginners. It presents a mathematical proof of what is the magnitude of an N-point discrete Fourier transform (DFT) when the DFT's input is a real-valued sinusoidal sequence.

To be specific, if we perform an N-point DFT on N real-valued time-domain samples of a discrete cosine wave, having exactly integer k cycles over N time samples, the peak magnitude of the cosine wave's...

## Compute the Frequency Response of a Multistage Decimator

Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1]. A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters. This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.

The frequency response of the single-stage decimator before downsampling is just...

## An Astounding Digital Filter Design Application

I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.

What I Liked About the ASN Filter DesignerWith typical filter design software packages the user enters numerical values for the...

## Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:

## Going back to Germany!

A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons. I came back from the conference energized and really happy that I went.

These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...

## A Fast Guaranteed-Stable Sliding DFT Algorithm

This blog presents a most computationally-efficient guaranteed-stable real-time sliding discrete Fourier transform (SDFT) algorithm. The phrase “real-time” means the network computes one spectral output sample, equal to a single-bin output of an N‑point discrete Fourier transform (DFT), for each input signal sample.

Proposed Guaranteed Stable SDFT

My proposed guaranteed stable SDFT, whose development is given in [1], is shown in Figure 1(a). The output sequence Xk(n) is an N-point...

## Design IIR Highpass Filters

This post is the fourth in a series of tutorials on IIR Butterworth filter design. So far we covered lowpass [1], bandpass [2], and band-reject [3] filters; now we’ll design highpass filters. The general approach, as before, has six steps:

Find the poles of a lowpass analog prototype filter with Ωc = 1 rad/s. Given the -3 dB frequency of the digital highpass filter, find the corresponding frequency of the analog highpass filter (pre-warping). Transform the...## Phase and Amplitude Calculation for a Pure Real Tone in a DFT: Method 1

IntroductionThis is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT) by deriving exact formulas for the phase and amplitude of a non-integer frequency real tone in a DFT. The linearity of the Fourier Transform is exploited to reframe the problem as the equivalent of finding a set of coordinates in a specific vector space. The found coordinates are then used to calculate the phase and amplitude of the pure real tone in the DFT. This article...

## Peak to Average Power Ratio and CCDF

Peak to Average Power Ratio (PAPR) is often used to characterize digitally modulated signals. One example application is setting the level of the signal in a digital modulator. Knowing PAPR allows setting the average power to a level that is just low enough to minimize clipping.

However, for a random signal, PAPR is a statistical quantity. We have to ask, what is the probability of a given peak power? Then we can decide where to set the average...

## Padé Delay is Okay Today

This article is going to be somewhat different in that I’m not really writing it for the typical embedded systems engineer. Rather it’s kind of a specialized topic, so don’t be surprised if you get bored and move on to something else. That’s fine by me.

Anyway, let’s just jump ahead to the punchline. Here’s a numerical simulation of a step response to a \( p=126, q=130 \) Padé approximation of a time delay:

Impressed? Maybe you should be. This...

## TCP/IP interface (Matlab/Octave)

Communicate with measurement instruments via Ethernet (no-toolbox-Matlab or Octave)

PurposeMeasurement automation is digital signal processing in a wider sense: Getting a digital signal from an analog world usually involves some measurement instruments, for example a spectrum analyzer. Modern instruments, and also many off-the-shelf prototyping boards such as FPGA cards [1] or microcontrollers [2] are able to communicate via Ethernet. Here, I provide some basic mex-functions (compiled C...

## A Simplified Matlab Function for Power Spectral Density

In an earlier post [1], I showed how to compute power spectral density (PSD) of a discrete-time signal using the Matlab function pwelch [2]. Pwelch is a useful function because it gives the correct output, and it has the option to average multiple Discrete Fourier Transforms (DFTs). However, a typical function call has five arguments, and it can be hard to remember how to set them all and how they default.

In this post, I create a simplified PSD function by putting a...

## Free Goodies from Embedded World - What to Do Next?

I told you I would go on a hunt for free stuff at Embedded World in order to build a bundle for someone to win.

## Sinusoidal Frequency Estimation Based on Time-Domain Samples

The topic of estimating a noise-free real or complex sinusoid's frequency, based on fast Fourier transform (FFT) samples, has been presented in recent blogs here on dsprelated.com. For completeness, it's worth knowing that simple frequency estimation algorithms exist that do not require FFTs to be performed . Below I present three frequency estimation algorithms that use time-domain samples, and illustrate a very important principle regarding so called "exact"...

## IIR Bandpass Filters Using Cascaded Biquads

In an earlier post [1], we implemented lowpass IIR filters using a cascade of second-order IIR filters, or biquads.

This post provides a Matlab function to do the same for Butterworth bandpass IIR filters. Compared to conventional implementations, bandpass filters based on biquads are less sensitive to coefficient quantization [2]. This becomes important when designing narrowband filters.

A biquad section block diagram using the Direct Form II structure [3,4] is...

## Signal Processing Contest in Python (PREVIEW): The Worst Encoder in the World

When I posted an article on estimating velocity from a position encoder, I got a number of responses. A few of them were of the form "Well, it's an interesting article, but at slow speeds why can't you just take the time between the encoder edges, and then...." My point was that there are lots of people out there which take this approach, and don't take into account that the time between encoder edges varies due to manufacturing errors in the encoder. For some reason this is a hard concept...