An s-Plane to z-Plane Mapping Example
A misleading online diagram prompted Rick Lyons to reexamine how s-plane points map to the z-plane. He spotted apparent errors in the original figure, drew a corrected mapping, and invites readers to inspect both diagrams and point out any remaining mistakes. The short post is a quick visual primer for engineers who rely on accurate s-plane to z-plane mappings in analysis and design.
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Rick Lyons argues z-transform regions of convergence are mostly a classroom abstraction with little practical use for real-world DSP engineers. For all stable LTI impulse responses encountered in practice the ROC includes the unit circle, so DTFT and DFT exist and ROC analysis rarely affects implementation. He notes digital oscillators are a notable exception, and suggests reallocating classroom time to more practical engineering topics.
Implementing Impractical Digital Filters
Some published IIR block diagrams are impossible to implement because they contain delay-less feedback paths, and Rick Lyons shows how simple algebra fixes that. He works through two concrete examples—a bandpass built from a FIR notch and a narrowband notch using a feedback loop—and derives equivalent, implementable second-order IIR transfer functions. The post emphasizes spotting problematic loops and replacing them with practical block diagrams.
An Astounding Digital Filter Design Application
Rick Lyons was astonished by the ASN Filter Designer, a hands-on filter design tool that makes tweaking frequency responses as simple as dragging markers with your mouse. The software updates magnitude plots, z-plane pole/zero locations, and filter coefficients in real time, and it also includes a signal analyzer plus a MATLAB-like scripting language for custom coefficient generation. The post links to a demo and user guides so you can try it yourself.
Digital PLL's -- Part 2
Neil Robertson builds a Z-domain model of a second-order digital PLL with a proportional-plus-integral loop filter, then derives closed-form formulas for KL and KI from the desired loop natural frequency and damping. The post explains the s → (z - 1)/Ts approximation, shows how to form the closed-loop IIR CL(z) for step and frequency responses, and highlights when the linear Z-domain model falls short of nonlinear acquisition behavior.
The Swiss Army Knife of Digital Networks
This blog describes a general discrete-signal network that appears, in various forms, inside so many DSP applications.
Figure 1 shows how the network's structure has the distinct look of a digital filter—a comb filter followed by a 2nd-order recursive network. However, I do not call this useful network a filter because its capabilities extend far beyond simple filtering. Through a series of examples I've illustrated the fundamental strength of this Swiss Army Knife of digital networks...
Digital PLL's -- Part 1
A hands-on introduction to time-domain digital phase-locked loops, Neil Robertson builds a simple DPLL model in MATLAB and walks through the NCO, phase detector, and PI loop filter implementations. The post uses phase-in-cycles arithmetic to show how the phase accumulator, detector wrapping, and loop filter interact, and it contrasts linear steady-state behavior with the nonlinear acquisition seen when initial frequency error is large. Part 2 will cover frequency-domain tuning of the loop gains.
Peak to Average Power Ratio and CCDF
Setting digital modulator levels depends on peak-to-average power ratio, because random signals produce occasional high peaks that cause clipping. This post shows how to compute the CCDF of PAPR from a signal vector, with MATLAB code and examples for a sine wave and Gaussian noise. The examples reveal the fixed 3.01 dB PAPR of a sine and the need for large sample counts to capture rare AWGN peaks.
Filter a Rectangular Pulse with no Ringing
You can filter a rectangular pulse with no ringing simply by using an FIR whose coefficients are all positive, and make them symmetric to get identical leading and trailing edges. This post walks through a MATLAB example that convolves a normalized Hanning window with a 32-sample rectangular pulse, showing that window length controls edge duration and that shorter windows widen the spectrum. It also notes this is not a QAM pulse-shaping solution.
Data Types for Control & DSP
Control engineers often default to double precision, but Tim Wescott shows that choice can waste CPU cycles on embedded targets. He separates numeric representation into floating point, integer, and fixed-point, then walks through the tradeoffs, including quantization, overflow, and performance. A concrete PID example highlights why integrator precision and ADC scaling should drive your choice of data type rather than habit.
DSPRelated and EmbeddedRelated now on Facebook & I will be at EE Live!
Stephane Boucher announces two practical updates for DSPRelated readers. He launched Facebook pages for DSPRelated and EmbeddedRelated so members can get faster updates, and he will be attending EE Live in San Jose from March 30 to April 3 with a $100-off promo code for early registration. He also asks the community for ideas on how to make his conference coverage most useful.
Reducing IIR Filter Computational Workload
Rick Lyons demonstrates a simple, practical way to cut the multiply count for IIR lowpass and highpass filters by converting them into dual-path allpass structures. The conversion preserves the original magnitude response while drastically reducing multiplies per input sample, for example turning a 5th-order IIR that needs 11 multiplies into an equivalent allpass form needing only five. The linked PDF includes theory, implementation notes, a design example, and MATLAB code.
A Narrow Bandpass Filter in Octave or Matlab
Building very narrow FIR bandpass filters at high sample rates often yields extremely long impulse responses. This post shows a practical Octave/Matlab implementation that uses complex downconversion to baseband plus a multistage Matrix IFIR and running-sum cascade to slash computation. With the provided example (48 kHz, 850 Hz center, 10 Hz passband) you get <1 dB ripple and >60 dB stopband while running 20x to 100x faster than a single-stage FIR.
Peak to Average Power Ratio and CCDF
Setting digital modulator levels depends on peak-to-average power ratio, because random signals produce occasional high peaks that cause clipping. This post shows how to compute the CCDF of PAPR from a signal vector, with MATLAB code and examples for a sine wave and Gaussian noise. The examples reveal the fixed 3.01 dB PAPR of a sine and the need for large sample counts to capture rare AWGN peaks.
Reduced-Delay IIR Filters
Rick Lyons investigates a simple 2nd-order IIR modification that reduces passband group delay by just under one sample, inspired by Steve Maslen's reduced-delay concept. He walks through the conversion steps and compares z-plane, magnitude, and group-delay plots for Butterworth, elliptic, and Chebyshev prototypes, showing how zeros shift and stopband attenuation degrades. A linked PDF extends the study to 1st-, 3rd-, and 4th-order cases so you can follow the tradeoffs.
Call for Speakers for the Inaugural Signal Processing Summit
Announcing the Call for Speakers for the inaugural Signal Processing Summit, happening October 14-16, 2025 in Silicon Valley. If you have practical, real-world DSP experience, including communications, audio, AI/ML, or core techniques, organizers want talks that are actionable and engineer-focused. Four tracks plus an open call for radar, imaging, biomedical, and sensor-system applications are listed; submit proposals by August 8, 2025.
Do Multirate Systems Have Transfer Functions?
Multirate systems can fool you into thinking standard z-domain analysis always applies. Rick Lyons shows why CIC decimation and Hogenauer implementations do not have a single z-domain transfer function from the input to the downsampled output, because downsampling breaks the one-to-one frequency mapping of LTI systems. Use the cascaded-subfilter H(z) up to the decimation point, then explicitly account for aliasing when predicting the decimated spectrum.
A Direct Digital Synthesizer with Arbitrary Modulus
Need exact sampled tones on a coarse grid without a huge sine table? This post shows how to build a Direct Digital Synthesizer with an arbitrary modulus so the output frequency is exactly k·fs/L, using a look-up table as small as 20 entries for the 10 MHz/0.5 MHz-step example. It also explains fixed-point LUT rounding, accumulator bit sizing, and how to produce quadrature outputs when L is multiple of 4.
TCP/IP interface (Matlab/Octave)
Markus Nentwig supplies a compact set of mex C functions that let you control Ethernet-enabled measurement instruments directly from Matlab or Octave on Windows. The code opens raw TCP/IP sockets, sends SCPI commands, and handles ASCII and binary replies including binary-length headers. It intentionally avoids instrument-control toolboxes and timeouts for simplicity, and includes instrIf_socket, instrIf_write, instrIf_read and instrIf_close with simple usage examples.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.
- Part 1: Introduction
- Part 2:...
Computing Translated Frequencies in Digitizing and Downsampling Analog Bandpass Signals
Textbooks rarely give ready formulas for tracking where individual spectral lines land after bandpass sampling or decimation. Rick Lyons provides three concise equations, with Matlab code, that compute translated frequencies for analog bandpass sampling, real digital downsampling, and complex downsampling. Practical examples show how to place the sampled image at fs/4 and how to translate a complex bandpass to baseband for efficient demodulation.
A multiuser waterfilling algorithm
Markus Nentwig shares a compact, heuristic multiuser waterfilling algorithm with ready-to-run C code, designed for practical radio resource allocation. The approach uses round-robin user handling, per-user power budgets and a mode switch between fixed-power and waterfilling distributions, and it is easy to extend for constraints or QoS tweaks. The implementation is suboptimal by design, fast, and requires verification before production use.
Multimedia Processing with FFMPEG
FFMPEG is a set of libraries and a command line tool for encoding and decoding audio and video in many different formats. It is a free software project for manipulating/processing multimedia data. Many open source media players are based on FFMPEG libraries.
Harmonic Notch Filter
A practical, DSP-friendly recipe for scrubbing 60 Hz power-line hum and its harmonics from noisy ECG and EEG recordings is presented, using IIR notch filters built from second-order all-pass sections. The post derives how to set all-pass phase to place notches and compute biquad coefficients by solving a simple 2x2 system, then shows C code and precomputed coefficients for cascading the first eight odd harmonics at a 2 kHz sample rate. Engineers get a compact, editable implementation with explicit control over notch bandwidth.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.
- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:
ESC Boston's Videos are Now Up
In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish. Here they are, please have a look and any feedback (positive or negative) is appreciated.
Short HighlightThis is a very short (one minute) montage of some of the footage that I shot at the show & conference. In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...
Discrete Wavelet Transform Filter Bank Implementation (part 2)
David Valencia walks through practical differences between the discrete wavelet transform and the discrete wavelet packet transform, showing why DWPT yields symmetric frequency resolution while DWT favors a single high-pass branch. He explains how Noble identities let you collapse multi-branch filter banks into equivalent single convolutions, then compares block convolution matrices with chain-processing and links to MATLAB code for both approaches.
Computing an FFT of Complex-Valued Data Using a Real-Only FFT Algorithm
Rick Lyons shows a compact trick to get an N-point complex FFT using only real-input FFT routines by transforming the real and imaginary parts separately and recombining their outputs. The post presents a one-line recombination formula, Xc(m) = real[Xr(m)] - imag[Xi(m)] + j{imag[Xr(m)] + real[Xi(m)]}, and an algebraic derivation based on the two-real-in-one-complex FFT identity. Useful for systems that only provide real-only FFTs.
Resolving 'Can't initialize target CPU' on TI C6000 DSPs - Part 2
Mike Dunn walks through practical, low-level debugging to fix "Can't initialize target CPU" on TI C6000 DSPs using CCS 3.3, focusing on XDS510-class emulators. He demonstrates how to run xdsprobe to perform JTAG resets, read and interpret adapter and port error messages, and run JTAG IR/DR integrity tests. The article shows example outputs and a simple scope-based trace to locate signal faults.
