Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

Steve Maslen August 22, 2017
Introduction to the topic 

This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

  • Part 1: 

Modeling a Continuous-Time System with Matlab

Neil Robertson June 6, 20172 comments

Many of us are familiar with modeling a continuous-time system in the frequency domain using its transfer function H(s) or H(jω).  However, finding the time response can be challenging, and traditionally involves finding the inverse Laplace transform of H(s).  An alternative way to get both time and frequency responses is to transform H(s) to a discrete-time system H(z) using the impulse-invariant transform [1,2].  This method provides an exact match to the continuous-time...


Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization

AHMED SHAHEIN March 1, 20176 comments

During my research on digital FIR decimation filters I have been developing various Matlab scripts and functions. In which I have decided later on to consolidate it in a form of a toolbox. I have developed this toolbox to assist and automate the process of designing the multi-stage decimation filter(s). The toolbox is published as an open-source at the MathWorks web-site. My dissertation is open for public online as well. The toolbox has a wide set of examples to guide the user...


Canonic Signed Digit (CSD) Representation of Integers

Neil Robertson February 18, 2017

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients.  I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values.  Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}.  Thus, for example, the binary value 1 1...


Matlab Code to Synthesize Multiplierless FIR Filters

Neil Robertson October 31, 20163 comments

This article presents Matlab code to synthesize multiplierless Finite Impulse Response (FIR) lowpass filters.

A filter coefficient can be represented as a sum of powers of 2.  For example, if a coefficient = decimal 5 multiplies input x, the output is $y= 2^2*x + 2^0*x$.  The factor of $2^2$ is then implemented with a shift of 2 bits.  This method is not efficient for coefficients having a lot of 1’s, e.g. decimal 31 = 11111.  To reduce the number of non-zero...


The Power Spectrum

Neil Robertson October 8, 2016

Often, when calculating the spectrum of a sampled signal, we are interested in relative powers, and we don’t care about the absolute accuracy of the y axis.  However, when the sampled signal represents an analog signal, we sometimes need an accurate picture of the analog signal’s power in the frequency domain.  This post shows how to calculate an accurate power spectrum.

Parseval’s theorem [1,2] is a property of the Discrete Fourier Transform (DFT) that...


Digital PLL's -- Part 2

Neil Robertson June 15, 20162 comments

In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter.  Now let’s look at this PLL in the Z-domain [1, 2].  We will find that the response is characterized by a loop natural frequency ωn and damping coefficient ζ. 

Having a Z-domain model of the DPLL will allow us to do three things:

Compute the values of loop filter proportional gain KL and integrator gain KI that give the desired loop natural...

Digital PLL's -- Part 1

Neil Robertson June 7, 201618 comments
1. Introduction

Figure 1.1 is a block diagram of a digital PLL (DPLL).  The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal.  The loop includes a phase detector to compute phase error and a loop filter to set loop dynamic performance.  The output of the loop filter controls the frequency and phase of the NCO, driving the phase error to zero.

One application of the DPLL is to recover the timing in a digital...


A poor man's Simulink

Markus Nentwig January 24, 20153 comments

Glue between Octave and NGSPICE for discrete- and continuous time cosimulation (download) Keywords: Octave, SPICE, Simulink

Introduction

Many DSP problems have close ties with the analog world. For example, a switched-mode audio power amplifier uses a digital control loop to open and close power transistors driving an analog filter. There are commercial tools for digital-analog cosimulation: Simulink comes to mind, and mainstream EDA vendors support VHDL-AMS or Verilog-A in their...


Spline interpolation

Markus Nentwig May 11, 20146 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...


Canonic Signed Digit (CSD) Representation of Integers

Neil Robertson February 18, 2017

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients.  I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values.  Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}.  Thus, for example, the binary value 1 1...


Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

Steve Maslen July 9, 2018

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.    

Fig 1. The evaluation platform

Additional design...


Radio Frequency Distortion Part II: A power spectrum model

Markus Nentwig October 11, 20101 comment
Summary

This article presents a ready-to-use model for nonlinear distortion caused by radio frequenfcy components in wireless receivers and linear transmitters. Compared to the similar model presented in my earlier blog entry, it operates on expectation values of the the power spectrum instead of the signal itself: Use the signal-based model to generate distortion on a signal, and the one from this article to directly obtain the power spectrum much more efficiently.In...


Bank-switched Farrow resampler

Markus Nentwig August 13, 2011
Bank-switched Farrow resampler Summary

A modification of the Farrow structure with reduced computational complexity.Compared to a conventional design, the impulse response is broken into a higher number of segments. Interpolation accuracy is achieved with a lower polynomial order, requiring fewer multiplications per output sample at the expense of a higher overall number of coefficients.

Example code

This code snippet provides a Matlab / Octave implementation.And


Correlation without pre-whitening is often misleading

Peter Kootsookos February 18, 20089 comments
White Lies

Correlation, as one of the first tools DSP users add to their tool box, can automate locating a known signal within a second (usually larger) signal. The expected result of a correlation is a nice sharp peak at the location of the known signal and few, if any, extraneous peaks.

A little thought will show this to be incorrect: correlating a signal with itself is only guaranteed to give a sharp peak if the signal's samples are uncorrelated --- for example if the signal is composed...


Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Neil Robertson May 27, 201823 comments

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA.  This situation is shown in Figure 1.  Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2.  This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1].  In that PLL, we...


Modeling a Continuous-Time System with Matlab

Neil Robertson June 6, 20172 comments

Many of us are familiar with modeling a continuous-time system in the frequency domain using its transfer function H(s) or H(jω).  However, finding the time response can be challenging, and traditionally involves finding the inverse Laplace transform of H(s).  An alternative way to get both time and frequency responses is to transform H(s) to a discrete-time system H(z) using the impulse-invariant transform [1,2].  This method provides an exact match to the continuous-time...


Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Steve Maslen August 24, 2017
Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.


Weighted least-squares FIR with shared coefficients

Markus Nentwig May 23, 2012

FIR design with arbitrary routing between delay line and coefficient multipliers.

Includes a commented implementation of a generic IRLS FIR design algorithm.

Introduction: Reverse Engineering

While looking for numerical IIR filter optimization, a Matlab program in [1] for the design of FIR filters caught my attention. The equations looked familiar, sort of, but on closer examination the pieces refused to fit together. Without the references, it took about two evenings to sort out how it...


ADC Clock Jitter Model, Part 2 – Random Jitter

Neil Robertson April 22, 20185 comments

In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter.  Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered Gaussian sequence as the jitter source.  What we are calling jitter can also be called time jitter, phase jitter, or phase noise.  It’s all the same phenomenon.  Typically, we call it jitter when we have a time-domain representation,...