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Polar Coding Notes: Channel Combining and Channel Splitting

Lyons Zhang October 19, 2018

Channel Combining  

Channel combining is a step that combines copies of a given B-DMC $W$ in a recursive manner to produce a vector channel $W_N : {\cal X}^N \to {\cal Y}^N$, where $N$ can be any power of two, $N=2^n, n\le0^{[1]}$.  

The notation $u_1^N$ as shorthand for denoting a row vector $(u_1, \dots , u_N)$.  

The vector channel $W_N$ is the virtual channel between the input sequence $u_1^N$ to a linear encoder and the output sequence $y^N_1$ of $N$...


Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo August 13, 20181 comment

The Google Summer of Code 2018 is now in its final stages, and I’d like to take a moment to look back at what goals were accomplished, what remains to be completed and what I have learnt.

The project overview was discussed in the previous blog posts. However this post serves as a guide to anyone who wishes to learn about the project or carry it forward. Hence I will go over the project details again.

Project overview

The project “Digital Filter Blocks in MyHDL and PyFDA integration" aims...


Sensors Expo - Trip Report & My Best Video Yet!

Stephane Boucher August 3, 20183 comments

This was my first time at Sensors Expo and my second time in Silicon Valley and I must say I had a great time.  

Before I share with you what I find to be, by far, my best 'highlights' video yet for a conference/trade show, let me try to entertain you with a few anecdotes from this trip.  If you are not interested by my stories or maybe don't have the extra minutes needed to read them, please feel free to skip to the end of this blog post to watch the...


Design a DAC sinx/x Corrector

Neil Robertson July 22, 20188 comments

This post provides a Matlab function that designs linear-phase FIR sinx/x correctors.  It includes a table of fixed-point sinx/x corrector coefficients for different DAC frequency ranges.

A sinx/x corrector is a digital (or analog) filter used to compensate for the sinx/x roll-off inherent in the digital to analog conversion process.  In DSP math, we treat the digital signal applied to the DAC is a sequence of impulses.  These are converted by the DAC into contiguous pulses...


Off Topic: Refraction in a Varying Medium

Cedron Dawg July 11, 20183 comments
Introduction

This article is another digression from a better understanding of the DFT. In fact, it is a digression from DSP altogether. However, since many of the readers here are Electrical Engineers and other folks who are very scientifically minded, I hope this article is of interest. A differential vector equation is derived for the trajectory of a point particle in a field of varying index of refraction. This applies to light, of course, but since it is a purely theoretical...


Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

Steve Maslen July 9, 2018

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.    

Fig 1. The evaluation platform

Additional design...


Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo July 9, 2018

This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks. 

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...


Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo June 22, 2018

This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.

  • Implementation of filter blocks in MyHDL
  • Design of interface between filter blocks and PyFDA

This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.

Direct form-I FIR filter

The equation specifies the direct form I...


Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction

Jason Sachs June 19, 2018

Last time, we talked about error correction and detection, covering some basics like Hamming distance, CRCs, and Hamming codes. If you are new to this topic, I would strongly suggest going back to read that article before this one.

This time we are going to cover Reed-Solomon codes. (I had meant to cover this topic in Part XV, but the article was getting to be too long, so I’ve split it roughly in half.) These are one of the workhorses of error-correction, and they are used in...


Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction

Jason Sachs June 12, 2018

Last time, we talked about Gold codes, a specially-constructed set of pseudorandom bit sequences (PRBS) with low mutual cross-correlation, which are used in many spread-spectrum communications systems, including the Global Positioning System.

This time we are wading into the field of error detection and correction, in particular CRCs and Hamming codes.

Ernie, You Have a Banana in Your Ear

I have had a really really tough time writing this article. I like the...


Spline interpolation

Markus Nentwig May 11, 20147 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...


Angle Addition Formulas from Euler's Formula

Cedron Dawg March 16, 20199 comments
Introduction

This is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT), but only indirectly. The main intent is to get someone who is uncomfortable with complex numbers a little more used to them and relate them back to already known Trigonometric relationships done in Real values. It is essentially a followup to my first blog article "The Exponential Nature of the Complex Unit Circle".

Polar Coordinates

The more common way of...


Instantaneous Frequency Measurement

Parth Vakil February 4, 200821 comments

I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. But, of course, with simplicity, there come drawbacks (sometimes...especially with this one!).

In the world of Radar detection and characterization, one of the key characteristics of interest is the carrier frequency of the signal. If the radar is pulsed, you will have a very wide bandwidth, a...


Should DSP Undergraduate Students Study z-Transform Regions of Convergence?

Rick Lyons September 14, 201613 comments

Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:

     "I noticed that you didn't discuss z-plane regions of      convergence here. In my undergraduate DSP class we      spent a lot of classroom and homework time on the  ...


Canonic Signed Digit (CSD) Representation of Integers

Neil Robertson February 18, 2017

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients.  I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values.  Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}.  Thus, for example, the binary value 1 1...


Correcting an Important Goertzel Filter Misconception

Rick Lyons July 6, 201517 comments

Recently I was on the Signal Processing Stack Exchange web site (a question and answer site for DSP people) and I read a posted question regarding Goertzel filters [1]. One of the subscribers posted a reply to the question by pointing interested readers to a Wikipedia web page discussing Goertzel filters [2]. I noticed the Wiki web site stated that a Goertzel filter:

"...is marginally stable and vulnerable tonumerical error accumulation when computed usinglow-precision arithmetic and...

A Simple Complex Down-conversion Scheme

Rick Lyons January 21, 20087 comments
Recently I was experimenting with complex down-conversion schemes. That is, generating an analytic (complex) version, centered at zero Hz, of a real bandpass signal that was originally centered at ±fs/4 (one fourth the sample rate). I managed to obtain one such scheme that is computationally efficient, and it might be of some mild interest to you guys. The simple complex down-conversion scheme is shown in Figure 1(a).

It works like this: say we have a real xR(n) input bandpass...


Compute the Frequency Response of a Multistage Decimator

Neil Robertson February 10, 20192 comments

Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1].  A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters.  This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.

The frequency response of the single-stage decimator before downsampling is just...


Half-band filter on Xilinx FPGA

Lyons Zhang November 30, 20105 comments
1. DSP48 Slice in Xilinx FPGA

There are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending on the device, but broadly similar.

Figure 1: A whole DSP48A1 Slice in Spartan6 (www.xilinx.com)

2. Symmetric Systolic Half-band FIR

Figure 2: Symmetric Systolic Half-band FIR Filter

3. Two-channel Symmetric Systolic Half-band FIR

  Figure 3: 2-Channel...


Return of the Delta-Sigma Modulators, Part 1: Modulation

Jason Sachs May 28, 20231 comment

About a decade ago, I wrote two articles:

Each of these are about delta-sigma modulation, but they’re short and sweet, and not very in-depth. And the 2013 article was really more about analog-to-digital converters. So we’re going to revisit the subject, this time with a lot more technical depth — in fact, I’ve had to split this...