Take Control of Noise with Spectral Averaging

Sam Shearman April 20, 20183 comments

Most engineers have seen the moment-to-moment fluctuations that are common with instantaneous measurements of a supposedly steady spectrum. You can see these fluctuations in magnitude and phase for each frequency bin of your spectrogram. Although major variations are certainly reason for concern, recall that we don’t live in an ideal, noise-free world. After verifying the integrity of your measurement setup by checking connections, sensors, wiring, and the like, you might conclude that the...

Linear Feedback Shift Registers for the Uninitiated, Part XIV: Gold Codes

Jason Sachs April 18, 2018

Last time we looked at some techniques using LFSR output for system identification, making use of the peculiar autocorrelation properties of pseudorandom bit sequences (PRBS) derived from an LFSR.

This time we’re going to jump back to the field of communications, to look at an invention called Gold codes and why a single maximum-length PRBS isn’t enough to save the world using spread-spectrum technology. We have to cover two little side discussions before we can get into Gold...

FFT Interpolation Based on FFT Samples: A Detective Story With a Surprise Ending

Rick Lyons April 16, 201841 comments

This blog presents several interesting things I recently learned regarding the estimation of a spectral value located at a frequency lying between previously computed FFT spectral samples. My curiosity about this FFT interpolation process was triggered by reading a spectrum analysis paper written by three astronomers [1].

My fixation on one equation in that paper led to the creation of this blog.


The notion of FFT interpolation is straightforward to describe. That is, for example,...

ADC Clock Jitter Model, Part 1 – Deterministic Jitter

Neil Robertson April 16, 201820 comments

Analog to digital converters (ADC’s) have several imperfections that affect communications signals, including thermal noise, differential nonlinearity, and sample clock jitter [1, 2].  As shown in Figure 1, the ADC has a sample/hold function that is clocked by a sample clock.  Jitter on the sample clock causes the sampling instants to vary from the ideal sample time.  This transfers the jitter from the sample clock to the input signal.

In this article, I present a Matlab...

Crowdfunding Articles?

Stephane Boucher April 12, 201828 comments

Many of you have the knowledge and talent to write technical articles that would benefit the EE community.  What is missing for most of you though, and very understandably so, is the time and motivation to do it.   

But what if you could make some money to compensate for your time spent on writing the article(s)?  Would some of you find the motivation and make the time?

I am thinking of implementing a system/mechanism that would allow the EE community to...

How precise is my measurement?

Sam Shearman March 28, 20183 comments

Some might argue that measurement is a blend of skepticism and faith. While time constraints might make you lean toward faith, some healthy engineering skepticism should bring you back to statistics. This article reviews some practical statistics that can help you satisfy one common question posed by skeptical engineers: “How precise is my measurement?” As we’ll see, by understanding how to answer it, you gain a degree of control over your measurement time.

An accurate, precise...

Embedded World 2018 - More Videos!

Stephane Boucher March 27, 20181 comment

After the interview videos last week, this week I am very happy to release two more videos taken at Embedded World 2018 and that I am proud of.  

For both videos, I made extensive use of my two new toys, a Zhiyun Crane Gimbal and a Sony a6300 camera.

The use of a gimbal like the Zhiyun makes a big difference in terms of making the footage look much more stable and cinematographic.

As for the Sony camera, it takes fantastic slow-motion footage and...

Phase or Frequency Shifter Using a Hilbert Transformer

Neil Robertson March 25, 201821 comments

In this article, we’ll describe how to use a Hilbert transformer to make a phase shifter or frequency shifter.  In either case, the input is a real signal and the output is a real signal.  We’ll use some simple Matlab code to simulate these systems.  After that, we’ll go into a little more detail on Hilbert transformer theory and design. 

Phase Shifter

A conceptual diagram of a phase shifter is shown in Figure 1, where the bold lines indicate complex...

Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

Steve Maslen March 21, 2018

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.

Additional design...

Embedded World 2018 - The Interviews

Stephane Boucher March 21, 2018

Once again this year, I had the chance to go to Embedded World in Nuremberg Germany.  And once again this year, I brought my video equipment to try and capture some of the most interesting things at the show.  

Something new this year, I asked Jacob Beningo if he would partner with me in doing interviews with a few vendors.  I would operate the camera while Jacob would ask the right questions to the vendors to make them talk about the key products/features that...

Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Neil Robertson May 27, 201834 comments

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA.  This situation is shown in Figure 1.  Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2.  This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1].  In that PLL, we...

Half-band filter on Xilinx FPGA

Lyons Zhang November 30, 20105 comments
1. DSP48 Slice in Xilinx FPGA

There are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending on the device, but broadly similar.

Figure 1: A whole DSP48A1 Slice in Spartan6 (www.xilinx.com)

2. Symmetric Systolic Half-band FIR

Figure 2: Symmetric Systolic Half-band FIR Filter

3. Two-channel Symmetric Systolic Half-band FIR

  Figure 3: 2-Channel...

An Astounding Digital Filter Design Application

Rick Lyons July 7, 201613 comments

I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.

What I Liked About the ASN Filter Designer

With typical filter design software packages the user enters numerical values for the...

Curse you, iPython Notebook!

Christopher Felton May 1, 20124 comments


First, I think ipython is great. I use it daily and always have an ipython terminal open.  But just recently, I was showing off the ipython 0.12 notebook and in the process created a lengthy example while demonstrating the cool features of the ipython notebook.  The example included LaTeX equations, plots, etc.  Since the notebook session was on something of relevance I decided to clean up the session and use it for the beginning of a report.

Canonic Signed Digit (CSD) Representation of Integers

Neil Robertson February 18, 2017

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients.  I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values.  Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}.  Thus, for example, the binary value 1 1...

The Swiss Army Knife of Digital Networks

Rick Lyons June 13, 20168 comments

This blog describes a general discrete-signal network that appears, in various forms, inside so many DSP applications. 

Figure 1 shows how the network's structure has the distinct look of a digital filter—a comb filter followed by a 2nd-order recursive network. However, I do not call this useful network a filter because its capabilities extend far beyond simple filtering. Through a series of examples I've illustrated the fundamental strength of this Swiss Army Knife of digital networks...

Frequency Translation by Way of Lowpass FIR Filtering

Rick Lyons February 4, 20175 comments

Some weeks ago a question appeared on the dsp.related Forum regarding the notion of translating a signal down in frequency and lowpass filtering in a single operation [1]. It is possible to implement such a process by embedding a discrete cosine sequence's values within the coefficients of a traditional lowpass FIR filter. I first learned about this process from Reference [2]. Here's the story.

Traditional Frequency Translation Prior To Filtering

Think about the process shown in...

Some Observations on Comparing Efficiency in Communication Systems

Eric Jacobsen March 17, 2011

Engineering is usually about managing efficiencies of one sort or another. One of my favorite working definitions of an engineer says, "An engineer is somebody who can do for a nickel what any damn fool can do for a dollar." In that case, the implication is that the cost is one of the characteristics being optimized. But cost isn't always the main efficiency metric, or at least the only one. Consider how a common transportation appliance, the automobile, is optimized...

Online DSP Classes: Why Such a High Dropout Rate?

Rick Lyons October 7, 201718 comments

Last year the IEEE Signal Processing Magazine published a lengthy article describing three university-sponsored online digital signal processing (DSP) courses [1]. The article detailed all the effort the professors expended in creating those courses and the courses' perceived values to students. 

However, one fact that struck me as important, but not thoroughly addressed in the article, was the shocking dropout rate of those online courses. For two of the courses the article's...

Demonstrating the Periodic Spectrum of a Sampled Signal Using the DFT

Neil Robertson March 9, 201920 comments

One of the basic DSP principles states that a sampled time signal has a periodic spectrum with period equal to the sample rate.  The derivation of can be found in textbooks [1,2].  You can also demonstrate this principle numerically using the Discrete Fourier Transform (DFT).

The DFT of the sampled signal x(n) is defined as:

$$X(k)=\sum_{n=0}^{N-1}x(n)e^{-j2\pi kn/N} \qquad (1)$$


X(k) = discrete frequency spectrum of time sequence x(n)