Compute the Frequency Response of a Multistage Decimator
Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1]. A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters. This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.
The frequency response of the single-stage decimator before downsampling is just...
Smaller DFTs from bigger DFTs
Introduction
Let's consider the following hypothetical situation: You have a sequence $x$ with $N/2$ points and a black box which can compute the DFT (Discrete Fourier Transform) of an $N$ point sequence. How will you use the black box to compute the $N/2$ point DFT of $x$? While the problem may appear to be a bit contrived, the answer(s) shed light on some basic yet insightful and useful properties of the DFT.
On a related note, the reverse problem of computing an $N$...
A Brief Introduction To Romberg Integration
This blog briefly describes a remarkable integration algorithm, called "Romberg integration." The algorithm is used in the field of numerical analysis but it's not so well-known in the world of DSP.
To show the power of Romberg integration, and to convince you to continue reading, consider the notion of estimating the area under the continuous x(t) = sin(t) curve based on the five x(n) samples represented by the dots in Figure 1.The results of performing a Trapezoidal Rule, a...
Use Matlab Function pwelch to Find Power Spectral Density – or Do It Yourself
In my last post, we saw that finding the spectrum of a signal requires several steps beyond computing the discrete Fourier transform (DFT)[1]. These include windowing the signal, taking the magnitude-squared of the DFT, and computing the vector of frequencies. The Matlab function pwelch [2] performs all these steps, and it also has the option to use DFT averaging to compute the so-called Welch power spectral density estimate [3,4].
In this article, I’ll present some...
Microprocessor Family Tree
Below is a little microprocessor history. Perhaps some of the ol' timers here will recognize a few of these integrated circuits. I have a special place in my heart for the Intel 8080 chip.
Image copied, without permission, from the now defunct Creative Computing magazine, Vol. 11, No. 6, June 1985.
A Markov View of the Phase Vocoder Part 2
Introduction
Last post we motivated the idea of viewing the classic phase vocoder as a Markov process. This was due to the fact that the input signal’s features are unknown to the computer, and the phase advancement for the next synthesis frame is entirely dependent on the phase advancement of the current frame. We will dive a bit deeper into this idea, and flesh out some details which we left untouched last week. This includes the effect our discrete Fourier transform has on the...
A Markov View of the Phase Vocoder Part 1
IntroductionHello! This is my first post on dsprelated.com. I have a blog that I run on my website, http://www.christianyostdsp.com. In order to engage with the larger DSP community, I'd like to occasionally post my more engineering heavy writing here and get your thoughts.
Today we will look at the phase vocoder from a different angle by bringing some probability into the discussion. This is the first part in a short series. Future posts will expand further upon the ideas...
Evaluate Window Functions for the Discrete Fourier Transform
The Discrete Fourier Transform (DFT) operates on a finite length time sequence to compute its spectrum. For a continuous signal like a sinewave, you need to capture a segment of the signal in order to perform the DFT. Usually, you also need to apply a window function to the captured signal before taking the DFT [1 - 3]. There are many different window functions and each produces a different approximation of the spectrum. In this post, we’ll present Matlab code that...
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.
Fig 1. Making a Transmission Line, with the Circuit Emulator
Additional...
Computing Large DFTs Using Small FFTs
It is possible to compute N-point discrete Fourier transforms (DFTs) using radix-2 fast Fourier transforms (FFTs) whose sizes are less than N. For example, let's say the largest size FFT software routine you have available is a 1024-point FFT. With the following trick you can combine the results of multiple 1024-point FFTs to compute DFTs whose sizes are greater than 1024.
The simplest form of this idea is computing an N-point DFT using two N/2-point FFT operations. Here's how the trick...
Compute Modulation Error Ratio (MER) for QAM
This post defines the Modulation Error Ratio (MER) for QAM signals, and shows how to compute it. As we’ll see, in the absence of impairments other than noise, the MER tracks the signal’s Carrier-to-Noise Ratio (over a limited range). A Matlab script at the end of the PDF version of this post computes MER for a simplified QAM-64 system.
Figure 1 is a simplified block diagram of a QAM system. The transmitter includes a source of QAM symbols, a root-Nyquist...
Why Time-Domain Zero Stuffing Produces Multiple Frequency-Domain Spectral Images
This blog explains why, in the process of time-domain interpolation (sample rate increase), zero stuffing a time sequence with zero-valued samples produces an increased-length time sequence whose spectrum contains replications of the original time sequence's spectrum.
Background
The traditional way to interpolate (sample rate increase) an x(n) time domain sequence is shown in Figure 1.
Figure 1
The '↑ L' operation in Figure 1 means to...
60-Hz Noise and Baseline Drift Reduction in ECG Signal Processing
Electrocardiogram (ECG) signals are obtained by monitoring the electrical activity of the human heart for medical diagnostic purposes [1]. This blog describes a very efficient digital filter used to reduce both 60 Hz AC power line noise and unwanted signal baseline drift that often contaminate ECG signals.
PDF_HERE
We'll first describe the ECG noise reduction filter and then examine the filter's performance in a real-world ECG signal filtering example.Proposed ECG Noise Reduction Digital...
Plotting Discrete-Time Signals
A discrete-time sinusoid can have frequency up to just shy of half the sample frequency. But if you try to plot the sinusoid, the result is not always recognizable. For example, if you plot a 9 Hz sinusoid sampled at 100 Hz, you get the result shown in the top of Figure 1, which looks like a sine. But if you plot a 35 Hz sinusoid sampled at 100 Hz, you get the bottom graph, which does not look like a sine when you connect the dots. We typically want the plot of a...
A Narrow Bandpass Filter in Octave or Matlab
The design of a very narrow bandpass FIR filter, coded in either Octave or Matlab, can prove challenging if a computationally-efficient filter is required. This is especially true if the sampling rate is high relative to the filter's center frequency. The most obvious filter design methods, using either window-based or Remez ( Parks-McClellan ) functions, can easily result in filters with many thousands of taps.
The filter to be described reduces the computational effort (and thus...
Off Topic: The True Gravitational Geodesic
The third of my off topic Physics series resulting in the true gravitational geodesic equation and some surprising results about gravity.
Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction
Last time, we talked about Gold codes, a specially-constructed set of pseudorandom bit sequences (PRBS) with low mutual cross-correlation, which are used in many spread-spectrum communications systems, including the Global Positioning System.
This time we are wading into the field of error detection and correction, in particular CRCs and Hamming codes.
Ernie, You Have a Banana in Your EarI have had a really really tough time writing this article. I like the...
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...
The DSP Online Conference - Right Around the Corner!
It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..
It all started with a post in the DSPRelated forum about three months ago. We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community. So my goal with the post in the forum was to see if...
Compute the Frequency Response of a Multistage Decimator
Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1]. A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters. This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.
The frequency response of the single-stage decimator before downsampling is just...
Design of an anti-aliasing filter for a DAC
Overview
- Octaveforge / Matlab design script. Download: here
- weighted numerical optimization of Laplace-domain transfer function
- linear-phase design, optimizes vector error (magnitude and phase)
- design process calculates and corrects group delay internally
- includes sinc() response of the sample-and-hold stage in the ADC
- optionally includes multiplierless FIR filter
Digital-to-analog conversion connects digital...
An Astounding Digital Filter Design Application
I've recently encountered a digital filter design application that astonished me with its design flexibility, capability, and ease of use. The software is called the "ASN Filter Designer." After experimenting with a demo version of this filter design software I was so impressed that I simply had publicize it to the subscribers here on dsprelated.com.
What I Liked About the ASN Filter DesignerWith typical filter design software packages the user enters numerical values for the...
Spline interpolation
A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog
IntroductionSplines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...
Canonic Signed Digit (CSD) Representation of Integers
In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values. Here I want to use that function to illustrate a few properties of CSD numbers.
In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}. Thus, for example, the binary value 1 1...
5G NR QC-LDPC Encoding Algorithm
3GPP 5G has been focused on structured LDPC codes known as quasi-cyclic low-density parity-check (QC-LDPC) codes, which exhibit advantages over other types of LDPC codes with respect to the hardware implementations of encoding and decoding using simple shift registers and logic circuits.
5G NR QC-LDPC Circulant Permutation MatrixA circular permutation matrix ${\bf I}(P_{i,j})$ of size $Z_c \times Z_c$ is obtained by circularly shifting the identity matrix $\bf I$ of...
Correcting an Important Goertzel Filter Misconception
Recently I was on the Signal Processing Stack Exchange web site (a question and answer site for DSP people) and I read a posted question regarding Goertzel filters [1]. One of the subscribers posted a reply to the question by pointing interested readers to a Wikipedia web page discussing Goertzel filters [2]. I noticed the Wiki web site stated that a Goertzel filter:
"...is marginally stable and vulnerable tonumerical error accumulation when computed usinglow-precision arithmetic and...Wavelets I - From Filter Banks to the Dilation Equation
This is the first in what I hope will be a series of posts about wavelets, particularly about the Fast Wavelet Transform (FWT). The FWT is extremely useful in practice and also very interesting from a theoretical point of view. Of course there are already plenty of resources, but I found them tending to be either simple implementation guides that do not touch on the many interesting and sometimes crucial connections. Or they are highly mathematical and definition-heavy, for a...
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:
"I noticed that you didn't discuss z-plane regions of convergence here. In my undergraduate DSP class we spent a lot of classroom and homework time on the ...
Data Types for Control & DSP
There's a lot of information out there on what data types to use for digital signal processing, but there's also a lot of confusion, so the topic bears repeating.
I recently posted an entry on PID control. In that article I glossed over the data types used by showing "double" in all of my example code. Numerically, this should work for most control problems, but it can be an extravagant use of processor resources. There ought to be a better way to determine what precision you need...
