## Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA

This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks.

So, why do we need to integrate and how do we go about it?

As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...

## Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA

This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.

This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.

Direct form-I FIR filterThe equation specifies the direct form I...

## Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction

Last time, we talked about error correction and detection, covering some basics like Hamming distance, CRCs, and Hamming codes. If you are new to this topic, I would strongly suggest going back to read that article before this one.

This time we are going to cover Reed-Solomon codes. (I had meant to cover this topic in Part XV, but the article was getting to be too long, so I’ve split it roughly in half.) These are one of the workhorses of error-correction, and they are used in...

## Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction

Last time, we talked about Gold codes, a specially-constructed set of pseudorandom bit sequences (PRBS) with low mutual cross-correlation, which are used in many spread-spectrum communications systems, including the Global Positioning System.

This time we are wading into the field of error detection and correction, in particular CRCs and Hamming codes.

Ernie, You Have a Banana in Your EarI have had a really really tough time writing this article. I like the...

## Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!

This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.

I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...

## Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock

Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...

## Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA

Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.

This blog-post is the first of many to come for the...

## Two Easy Ways To Test Multistage CIC Decimation Filters

This blog presents two very easy ways to test the performance of multistage cascaded integrator-comb (CIC) decimation filters [1]. Anyone implementing CIC filters should take note of the following proposed CIC filter test methods.

Introduction

Figure 1 presents a multistage decimate by D CIC filter where the number of stages is S = 3. The '↓D' operation represents downsampling by integer D (discard all but every Dth sample), n is the input time index, and m is the output time index.

## ADC Clock Jitter Model, Part 2 – Random Jitter

In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered Gaussian sequence as the jitter source. What we are calling jitter can also be called time jitter, phase jitter, or phase noise. It’s all the same phenomenon. Typically, we call it jitter when we have a time-domain representation,...

## Take Control of Noise with Spectral Averaging

Most engineers have seen the moment-to-moment fluctuations that are common with instantaneous measurements of a supposedly steady spectrum. You can see these fluctuations in magnitude and phase for each frequency bin of your spectrogram. Although major variations are certainly reason for concern, recall that we don’t live in an ideal, noise-free world. After verifying the integrity of your measurement setup by checking connections, sensors, wiring, and the like, you might conclude that the...

## Went 280km/h (174mph) in a Porsche Panamera in Germany!

Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.

## A Simple Complex Down-conversion Scheme

Recently I was experimenting with complex down-conversion schemes. That is, generating an analytic (complex) version, centered at zero Hz, of a real bandpass signal that was originally centered at ±fs/4 (one fourth the sample rate). I managed to obtain one such scheme that is computationally efficient, and it might be of some mild interest to you guys. The simple complex down-conversion scheme is shown in Figure 1(a).It works like this: say we have a real xR(n) input bandpass...

## A Fast Guaranteed-Stable Sliding DFT Algorithm

This blog presents a most computationally-efficient guaranteed-stable real-time sliding discrete Fourier transform (SDFT) algorithm. The phrase “real-time” means the network computes one spectral output sample, equal to a single-bin output of an N‑point discrete Fourier transform (DFT), for each input signal sample.

Proposed Guaranteed Stable SDFT

My proposed guaranteed stable SDFT, whose development is given in [1], is shown in Figure 1(a). The output sequence Xk(n) is an N-point...

## Demonstrating the Periodic Spectrum of a Sampled Signal Using the DFT

One of the basic DSP principles states that a sampled time signal has a periodic spectrum with period equal to the sample rate. The derivation of can be found in textbooks [1,2]. You can also demonstrate this principle numerically using the Discrete Fourier Transform (DFT).

The DFT of the sampled signal x(n) is defined as:

$$X(k)=\sum_{n=0}^{N-1}x(n)e^{-j2\pi kn/N} \qquad (1)$$

Where

X(k) = discrete frequency spectrum of time sequence x(n)

## Dealing With Fixed Point Fractions

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...

## Ten Little Algorithms, Part 6: Green’s Theorem and Swept-Area Detection

Other articles in this series:

- Part 1: Russian Peasant Multiplication
- Part 2: The Single-Pole Low-Pass Filter
- Part 3: Welford's Method (And Friends)
- Part 4: Topological Sort
- Part 5: Quadratic Extremum Interpolation and Chandrupatla's Method

This article is mainly an excuse to scribble down some cryptic-looking mathematics — Don’t panic! Close your eyes and scroll down if you feel nauseous — and...

## Linear Feedback Shift Registers for the Uninitiated, Part XIV: Gold Codes

Last time we looked at some techniques using LFSR output for system identification, making use of the peculiar autocorrelation properties of pseudorandom bit sequences (PRBS) derived from an LFSR.

This time we’re going to jump back to the field of communications, to look at an invention called Gold codes and why a single maximum-length PRBS isn’t enough to save the world using spread-spectrum technology. We have to cover two little side discussions before we can get into Gold...

## Pulse Shaping in Single-Carrier Communication Systems

Some common conceptual hurdles for beginning communications engineers have to do with "Pulse Shaping" or the closely-related, even synonymous, topics of "matched filtering", "Nyquist filtering", "Nyquist pulse", "pulse filtering", "spectral shaping", etc. Some of the confusion comes from the use of terms like "matched filter" which has a broader meaning in the more general field of signal processing or detection theory. Likewise "Raised Cosine" has a different meaning or application in this...

## Do Multirate Systems Have Transfer Functions?

The following text describes why I ask the strange question in the title of this blog. Some months ago I was asked to review a article manuscript, for possible publication in a signal processing journal, that presented a method for improving the performance of cascaded integrator-comb (CIC) decimation filters [1].

Thinking about such filters, Figure 1(a) shows the block diagram of a traditional 2nd-order CIC decimation filter followed by downsampling by the sample rate factor R. There we...

## Sonos, Shut Up and Take My Money! - Is Spatial Audio Finally Here?

Although I generally agree that money can't buy happiness, I recently made a purchase that has brought me countless hours of pure joy. In this blog post, I want to share my excitement with the DSPRelated community, because I know there are many audio and music enthusiasts here, and also because I suspect there is a lot of DSP magic behind this product. And I would love to hear your opinions and experiences if you have also bought or tried the Sonos ERA 300 wireless speaker, or any other...

## The DSP Online Conference - Right Around the Corner!

It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..

It all started with a post in the DSPRelated forum about three months ago. We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community. So my goal with the post in the forum was to see if...

## Instantaneous Frequency Measurement

I would like to talk about the oft used method of measuring the carrier frequency in the world of Signal Collection and Characterization world. It is an elegant technique because of its simplicity. But, of course, with simplicity, there come drawbacks (sometimes...especially with this one!).

In the world of Radar detection and characterization, one of the key characteristics of interest is the carrier frequency of the signal. If the radar is pulsed, you will have a very wide bandwidth, a...

## Should DSP Undergraduate Students Study z-Transform Regions of Convergence?

Not long ago I presented my 3-day DSP class to a group of engineers at Tektronix Inc. in Beaverton Oregon [1]. After I finished covering my material on IIR filters' z-plane pole locations and filter stability, one of the Tektronix engineers asked a question similar to:

"I noticed that you didn't discuss z-plane regions of convergence here. In my undergraduate DSP class we spent a lot of classroom and homework time on the ...

## Correcting an Important Goertzel Filter Misconception

Recently I was on the Signal Processing Stack Exchange web site (a question and answer site for DSP people) and I read a posted question regarding Goertzel filters [1]. One of the subscribers posted a reply to the question by pointing interested readers to a Wikipedia web page discussing Goertzel filters [2]. I noticed the Wiki web site stated that a Goertzel filter:

"...is marginally stable and vulnerable tonumerical error accumulation when computed usinglow-precision arithmetic and...## Angle Addition Formulas from Euler's Formula

IntroductionThis is an article to hopefully give a better understanding of the Discrete Fourier Transform (DFT), but only indirectly. The main intent is to get someone who is uncomfortable with complex numbers a little more used to them and relate them back to already known Trigonometric relationships done in Real values. It is essentially a followup to my first blog article "The Exponential Nature of the Complex Unit Circle".

Polar CoordinatesThe more common way of...

## Canonic Signed Digit (CSD) Representation of Integers

In my last post I presented Matlab code to synthesize multiplierless FIR filters using Canonic Signed Digit (CSD) coefficients. I included a function dec2csd1.m (repeated here in Appendix A) to convert decimal integers to binary CSD values. Here I want to use that function to illustrate a few properties of CSD numbers.

In a binary signed-digit number system, we allow each binary digit to have one of the three values {0, 1, -1}. Thus, for example, the binary value 1 1...

## A Simple Complex Down-conversion Scheme

Recently I was experimenting with complex down-conversion schemes. That is, generating an analytic (complex) version, centered at zero Hz, of a real bandpass signal that was originally centered at ±fs/4 (one fourth the sample rate). I managed to obtain one such scheme that is computationally efficient, and it might be of some mild interest to you guys. The simple complex down-conversion scheme is shown in Figure 1(a).It works like this: say we have a real xR(n) input bandpass...

## Half-band filter on Xilinx FPGA

1. DSP48 Slice in Xilinx FPGAThere are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending on the device, but broadly similar.

Figure 1: A whole DSP48A1 Slice in Spartan6 (www.xilinx.com)

2. Symmetric Systolic Half-band FIRFigure 2: Symmetric Systolic Half-band FIR Filter

3. Two-channel Symmetric Systolic Half-band FIRFigure 3: 2-Channel...

## Compute the Frequency Response of a Multistage Decimator

Figure 1a shows the block diagram of a decimation-by-8 filter, consisting of a low-pass finite impulse response (FIR) filter followed by downsampling by 8 [1]. A more efficient version is shown in Figure 1b, which uses three cascaded decimate-by-two filters. This implementation has the advantages that only FIR 1 is sampled at the highest sample rate, and the total number of filter taps is lower.

The frequency response of the single-stage decimator before downsampling is just...

## Amplitude modulation and the sampling theorem

I am working on the 11th and probably final chapter of Think DSP, which follows material my colleague Siddhartan Govindasamy developed for a class at Olin College. He introduces amplitude modulation as a clever way to sneak up on the Nyquist–Shannon sampling theorem.

Most of the code for the chapter is done: you can check it out in this IPython notebook. I haven't written the text yet, but I'll outline it here, and paste in the key figures.

Convolution...