Evaluate Window Functions for the Discrete Fourier Transform
Spectral leakage makes DFTs of continuous sinewaves misleading, and windowing is the practical workaround. This post supplies Matlab code to plot spectra of windowed sinewaves and compute figures of merit, so you can compare windows such as flattop and Chebyshev. See how sidelobe level, mainlobe bandwidth, processing loss, noise bandwidth, and scallop loss trade off to guide your window choice.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Polar Coding Notes: A Simple Proof
Lyons Zhang presents a compact, elementary derivation of channel polarization for binary-input discrete memoryless channels. The note leverages Mrs. Gerber's Lemma to bound conditional entropies and follows the Alsan-Telatar averaging argument to show mediocre channels vanish. The proof sidesteps martingale convergence and recovers the standard result that the fraction of good channels approaches the channel capacity.
Polar Coding Notes: Channel Combining and Channel Splitting
Lyons Zhang walks through the core algebra of polar coding, showing how channel combining builds the vector channel W_N from N copies of a binary-input DMC using the polar transform G_N = B_N F^{⊗n}. The notes then define channel splitting, derive the coordinate-channel transition probabilities from the chain rule, and present the recursive formulas that let you compute W_{2N}^{(2i-1)} and W_{2N}^{(2i)} from W_N^{(i)}.
Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA
This Summer of Code project shows how to move from Python filter design to synthesizable HDL by building a MyHDL "filter-blocks" package and connecting it to PyFDA. The author implemented direct form I FIR and IIR blocks, added an API, tests, tutorials, and PyFDA export to VHDL and Verilog. The report also highlights practical fixed-point design choices and remaining work such as second-order sections.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
Design a DAC sinx/x Corrector
Neil Robertson provides a compact Matlab function and coefficient tables for designing linear-phase FIR sinx/x correctors to undo the DAC sinc roll-off. The post explains the sinc_corr(ntaps,fmax,fs) call, shows worked examples with ntaps=5 and different fmax values, and demonstrates fixed-point quantization including a k=512 example and CSD digit guidance. Practical notes cover corrector gain and input back-off to avoid clipping.
Off Topic: Refraction in a Varying Medium
Cedron Dawg derives a compact vector differential equation for a point particle moving through a smoothly varying refractive medium using the Euler-Lagrange variational method. By introducing a log refractive index called "fluff density," the paper expresses acceleration purely in terms of the fluff gradient and velocity, then explores curvature, superposition, and point-source capture radii with simple closed-form results.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This update shows a working integration between Pyfda and MyHDL using a compact API that passes fixed-point coefficients, stimulus data, and returns simulated filter responses. It walks through two usage styles, constructor-based and setter-method-based, and demonstrates a Pyfda workflow from specs to MyHDL simulation and plotting. Future plans include HDL code generation and API extension as filters grow.
Waveforms that are their own Fourier Transform
Steve Smith admits a long-standing mistake and overturns the claim that only Gaussians are their own Fourier transform. He gives trivial and nontrivial examples, explains why infinitely many such waveforms exist, and shows a quick discrete construction using the DFT with a 1/sqrt(N) normalization. Engineers get an intuitive 30-second argument plus a practical recipe to build self-Fourier signals.
Why Time-Domain Zero Stuffing Produces Multiple Frequency-Domain Spectral Images
Zero stuffing in the time domain creates spectral copies, and Rick Lyons walks through why that happens using DFT and DFS viewpoints. He shows that inserting L-1 zeros between samples yields a longer DFT with replicated spectral blocks, and that true interpolation requires lowpass filtering to remove those images. The post uses a concrete L=3 example and an inverse-DFT summation proof to make the effect intuitive.
Simple Concepts Explained: Fixed-Point
Fixed-point is the bridge between real-world values and integer arithmetic, and this post makes that bridge tangible with a hands-on ADC-to-gain example. It walks through mapping voltages to Q-format integers, choosing gain resolution in bits, and how multiplication adds bit growth and produces quantization error. Read it to build intuition for practical fixed-point choices when implementing DSP on FPGA or ASIC.
Padé Delay is Okay Today
High-order Padé approximations for time delays break in surprising ways, but the failure is not magic. Jason Sachs walks through why coefficient-based transfer functions and companion-form state-space are numerically fragile, shows how to compute poles and zeros directly from the hypergeometric form with Newton iteration, and demonstrates building modal or block-diagonal state-space realizations to make high-order Padé delays practical while noting remaining limits.
Discrete-Time PLLs, Part 1: Basics
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Python scipy.signal IIR Filter Design Cont.
Christopher Felton continues his practical tour of SciPy's iirdesign, moving beyond lowpass examples to show highpass, bandpass, and stopband designs with concise, code-focused explanations. He highlights how ellip and cheby2 let you tighten specifications for sharper transitions, and shows that the iirdesign workflow is consistent across filter types. Read for clear, reusable examples to produce IIR filter coefficients with scipy.signal.
TI goes the Open Source way!
TI has started opening parts of its toolchain by releasing a free standalone compiler for its C54x line, announced through Googles Summer of Code. Praveen Raghavan points out the bundle includes a compiler, optimizer, assembler, and linker but no debugger, and shows why this can enable open-source codec work on DM320-based OSD projects. The post calls for industry and academia to collaborate on improving compilers.
Learn About Transmission Lines Using a Discrete-Time Model
A simple discrete-time approach makes lossless transmission-line behavior easy to simulate and visualize. The post introduces MATLAB functions tline and wave_movie to model uniform lossless lines with resistive terminations, compute time and frequency responses, and animate travelling waves. A microstrip pulse example shows how reflections produce ringing and how source matching nearly eliminates it, making this a practical learning tool.
Engineering the Statistics
Statistical analysis can get messy fast when theory and MATLAB simulations refuse to agree. This post shares a graduate student’s hard-earned shortcuts for taming random variables, from deriving a CDF or moments to using Gaussian or Gamma approximations, and falling back on Chernoff bounds when the exact PDF stays out of reach.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Demonstrating the Periodic Spectrum of a Sampled Signal Using the DFT
This post makes a basic DSP principle tangible by computing the DFT over an extended set of bins and plotting the results. It demonstrates that a sampled signal's spectrum repeats every sampling rate, explains the k-to-frequency mapping, and contrasts common bin ranges such as 0..N-1 and -N/2..N/2-1. The write-up also highlights symmetry for real sequences and recommends using the FFT for efficiency.
DAC Zero-Order Hold Models
This article provides two simple time-domain models of a DAC’s zero-order hold. These models will allow us to find time and frequency domain approximations of DAC outputs, and simulate analog filtering of those outputs. Developing the models is also a good way to learn about the DAC ZOH function.
Correcting an Important Goertzel Filter Misconception
A common claim says the Goertzel algorithm is marginally stable and prone to numerical errors. Rick Lyons shows that the usual second-order Goertzel filter has conjugate poles exactly on the unit circle, so pole placement alone does not make it unstable. The practical limits are coefficient quantization, which reduces frequency precision, and accumulator overflow for very large N.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Rick Lyons argues z-transform regions of convergence are mostly a classroom abstraction with little practical use for real-world DSP engineers. For all stable LTI impulse responses encountered in practice the ROC includes the unit circle, so DTFT and DFT exist and ROC analysis rarely affects implementation. He notes digital oscillators are a notable exception, and suggests reallocating classroom time to more practical engineering topics.
A Simple Complex Down-conversion Scheme
Rick Lyons shows a compact way to turn a real bandpass signal centered at ±fs/4 into a complex, zero-centered analytic signal. The trick uses a delay, a Hilbert transform filter, and a 4:1 downsample, with a small compensation filter to widen the usable passband. He also points out a no-multiplier implementation using shift-and-add coefficients, or a higher-attenuation version with two multiplies per output sample.
How precise is my measurement?
Precision is quantifiable, not guesswork. This post walks through practical, measurement-oriented statistics you can apply to static or dynamic signals to answer the question, "How precise is my measurement?" It focuses on using multiple samples, checking distribution assumptions, and constructing confidence intervals and levels so you can trade measurement time for a desired precision.
Discrete Wavelet Transform Filter Bank Implementation (part 1)
David Valencia walks through a practical implementation of discrete wavelet transform filter banks, focusing on cascading branches and efficient equivalent filters. He contrasts DWT and DFT resolution behavior and shows how cascading the low-pass branch sharpens frequency division while the high-pass path remains unchanged. Code pointers and a preview of formfilters() demonstrate how to compute only the needed samples by combining filters with upsampling.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
