Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This is an exciting update in the sense that it demonstrates a working model of one important aspect of the project: The integration or ‘glue’ between and Pyfda and MyHDL filter blocks.
So, why do we need to integrate and how do we go about it?
As discussed in earlier posts, the idea is to provide a workflow in Pyfda that automates the process of Implementing a fixpoint filter in VHDL / Verilog, and verify the correct performance in a digital design environment. MyHDL based...
Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This blog post presents the progress made up to week 5 in my GSoC project “Digital Filter blocks and their integration in PyFDA”. Progress was made in two areas of the project.
This post will primarily discuss filter block implementation. The interface will be discussed in a later post once further progress is made.
Direct form-I FIR filterThe equation specifies the direct form I...
Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction
Last time, we talked about error correction and detection, covering some basics like Hamming distance, CRCs, and Hamming codes. If you are new to this topic, I would strongly suggest going back to read that article before this one.
This time we are going to cover Reed-Solomon codes. (I had meant to cover this topic in Part XV, but the article was getting to be too long, so I’ve split it roughly in half.) These are one of the workhorses of error-correction, and they are used in...
Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction
Last time, we talked about Gold codes, a specially-constructed set of pseudorandom bit sequences (PRBS) with low mutual cross-correlation, which are used in many spread-spectrum communications systems, including the Global Positioning System.
This time we are wading into the field of error detection and correction, in particular CRCs and Hamming codes.
Ernie, You Have a Banana in Your EarI have had a really really tough time writing this article. I like the...
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.
I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...
Digital PLL’s, Part 3 – Phase Lock an NCO to an External Clock
Sometimes you may need to phase-lock a numerically controlled oscillator (NCO) to an external clock that is not related to the system clocks of your ASIC or FPGA. This situation is shown in Figure 1. Assuming your system has an analog-to-digital converter (ADC) available, you can sync to the external clock using the scheme shown in Figure 2. This time-domain PLL model is similar to the one presented in Part 1 of this series on digital PLL’s [1]. In that PLL, we...
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.
This blog-post is the first of many to come for the...
Two Easy Ways To Test Multistage CIC Decimation Filters
This blog presents two very easy ways to test the performance of multistage cascaded integrator-comb (CIC) decimation filters [1]. Anyone implementing CIC filters should take note of the following proposed CIC filter test methods.
Introduction
Figure 1 presents a multistage decimate by D CIC filter where the number of stages is S = 3. The '↓D' operation represents downsampling by integer D (discard all but every Dth sample), and n is the time index.
If the Figure 3 filter's...
ADC Clock Jitter Model, Part 2 – Random Jitter
In Part 1, I presented a Matlab function to model an ADC with jitter on the sample clock, and applied it to examples with deterministic jitter. Now we’ll investigate an ADC with random clock jitter, by using a filtered or unfiltered Gaussian sequence as the jitter source. What we are calling jitter can also be called time jitter, phase jitter, or phase noise. It’s all the same phenomenon. Typically, we call it jitter when we have a time-domain representation,...
Take Control of Noise with Spectral Averaging
Most engineers have seen the moment-to-moment fluctuations that are common with instantaneous measurements of a supposedly steady spectrum. You can see these fluctuations in magnitude and phase for each frequency bin of your spectrogram. Although major variations are certainly reason for concern, recall that we don’t live in an ideal, noise-free world. After verifying the integrity of your measurement setup by checking connections, sensors, wiring, and the like, you might conclude that the...
Computing Large DFTs Using Small FFTs
It is possible to compute N-point discrete Fourier transforms (DFTs) using radix-2 fast Fourier transforms (FFTs) whose sizes are less than N. For example, let's say the largest size FFT software routine you have available is a 1024-point FFT. With the following trick you can combine the results of multiple 1024-point FFTs to compute DFTs whose sizes are greater than 1024.
The simplest form of this idea is computing an N-point DFT using two N/2-point FFT operations. Here's how the trick...
Linear-phase DC Removal Filter
This blog describes several DC removal networks that might be of interest to the dsprelated.com readers.
Back in August 2007 there was a thread on the comp.dsp newsgroup concerning the process of removing the DC (zero Hz) component from a time-domain sequence [1]. Discussed in that thread was the notion of removing a signal's DC bias by subtracting the signal's moving average from that signal, as shown in Figure 1(a).
Figure 1.
At first I thought...
Music/Audio Signal Processing
Greetings,
This is my blog from the point of view of a music/audio DSP research engineer / educator. It is informal and largely nontechnical because nearly everything I have to say about signal processing is (or will be) somewhere in my four-book series: Mathematics of DFT with Audio Applications, Introduction to Digital Filters, Physical Audio Signal Processing and
Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date
Chances are that you already know that I went to Embedded World a few weeks ago and came back with a bag full of "goodies". Initially, my vision was to do a single draw for one person to win it all, but I didn't expect to come back with so much stuff and so many development kits. Based on your feedback, it seems like you guys agree that It wouldn't make sense for one person to win everything as no-one could make good use of all the boards and there would be lots of...
Polyphase filter / Farrows interpolation
Hello,
this article is meant to give a quick overview over polyphase filtering and Farrows interpolation.
A good reference with more depth is for example Fred Harris' paper: http://www.signumconcepts.com/IP_center/paper018.pdf
The task is as follows: Interpolate a band-limited discrete-time signal at a variable offset between samples.In other words:Delay the signal by a given amount with sub-sample accuracy.Both mean the same.
The picture below shows samples (black) representing...
Design IIR Highpass Filters
This post is the fourth in a series of tutorials on IIR Butterworth filter design. So far we covered lowpass [1], bandpass [2], and band-reject [3] filters; now we’ll design highpass filters. The general approach, as before, has six steps:
Find the poles of a lowpass analog prototype filter with Ωc = 1 rad/s. Given the -3 dB frequency of the digital highpass filter, find the corresponding frequency of the analog highpass filter (pre-warping). Transform the...Free DSP Books on the Internet
While surfing the "net" I have occasionally encountered signal processing books whose chapters could be downloaded to my computer. I started keeping a list of those books and, over the years, that list has grown to over forty books. Perhaps the list will be of interest to you.
Please know, all of the listed books are copyrighted. The copyright holders have graciously provided their books free of charge for downloading for individual use, but multiple copies must not be made or printed. As...
Somewhat Off Topic: Deciphering Transistor Terminology
I recently learned something mildly interesting about transistors, so I thought I'd share my new knowledge with you folks. Figure 1 shows a p-n-p transistor comprising a small block of n-type semiconductor sandwiched between two blocks of p-type semiconductor.
The terminology of "emitter" and "collector" seems appropriate, but did you ever wonder why the semiconductor block in the center is called the "base"? The word base seems inappropriate because the definition of the word base is:...
Frequency Dependence in Free Space Propagation
Introduction
It seems to be fairly common knowledge, even among practicing professionals, that the efficiency of propagation of wireless signals is frequency dependent. Generally it is believed that lower frequencies are desirable since pathloss effects will be less than they would be at higher frequencies. As evidence of this, the Friis Transmission Equation[i] is often cited, the general form of which is usually written as:
Pr = Pt Gt Gr ( λ / 4πd )2 (1)
where the...
Digital PLL's -- Part 1
1. IntroductionFigure 1.1 is a block diagram of a digital PLL (DPLL). The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal. The loop includes a phase detector to compute phase error and a loop filter to set loop dynamic performance. The output of the loop filter controls the frequency and phase of the NCO, driving the phase error to zero.
One application of the DPLL is to recover the timing in a digital...
TCP/IP interface (Matlab/Octave)
Communicate with measurement instruments via Ethernet (no-toolbox-Matlab or Octave)
PurposeMeasurement automation is digital signal processing in a wider sense: Getting a digital signal from an analog world usually involves some measurement instruments, for example a spectrum analyzer. Modern instruments, and also many off-the-shelf prototyping boards such as FPGA cards [1] or microcontrollers [2] are able to communicate via Ethernet. Here, I provide some basic mex-functions (compiled C...
Generating pink noise
In one of his most famous columns for Scientific American, Martin Gardner wrote about pink noise and its relation to fractal music. The article was based on a 1978 paper by Voss and Clarke, which presents, among other things, a simple algorithm for generating pink noise, also known as 1/f noise.
The fundamental idea of the algorithm is to add up several sequences of uniform random numbers that get updated at different rates. The first source gets updated at...
Digital PLL's -- Part 1
1. IntroductionFigure 1.1 is a block diagram of a digital PLL (DPLL). The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal. The loop includes a phase detector to compute phase error and a loop filter to set loop dynamic performance. The output of the loop filter controls the frequency and phase of the NCO, driving the phase error to zero.
One application of the DPLL is to recover the timing in a digital...
How Discrete Signal Interpolation Improves D/A Conversion
This blog post is also available in pdf format. Download here.Earlier this year, for the Linear Audio magazine, published in the Netherlands whose subscribers are technically-skilled hi-fi audio enthusiasts, I wrote an article on the fundamentals of interpolation as it's used to improve the performance of analog-to-digital conversion. Perhaps that article will be of some value to the subscribers of dsprelated.com. Here's what I wrote:
We encounter the process of digital-to-analog...
Computing Large DFTs Using Small FFTs
It is possible to compute N-point discrete Fourier transforms (DFTs) using radix-2 fast Fourier transforms (FFTs) whose sizes are less than N. For example, let's say the largest size FFT software routine you have available is a 1024-point FFT. With the following trick you can combine the results of multiple 1024-point FFTs to compute DFTs whose sizes are greater than 1024.
The simplest form of this idea is computing an N-point DFT using two N/2-point FFT operations. Here's how the trick...
Sinusoidal Frequency Estimation Based on Time-Domain Samples
The topic of estimating a noise-free real or complex sinusoid's frequency, based on fast Fourier transform (FFT) samples, has been presented in recent blogs here on dsprelated.com. For completeness, it's worth knowing that simple frequency estimation algorithms exist that do not require FFTs to be performed . Below I present three frequency estimation algorithms that use time-domain samples, and illustrate a very important principle regarding so called "exact"...
Design IIR Bandpass Filters
In this post, I present a method to design Butterworth IIR bandpass filters. My previous post [1] covered lowpass IIR filter design, and provided a Matlab function to design them. Here, we’ll do the same thing for IIR bandpass filters, with a Matlab function bp_synth.m. Here is an example function call for a bandpass filter based on a 3rd order lowpass prototype:
N= 3; % order of prototype LPF fcenter= 22.5; % Hz center frequency, Hz bw= 5; ...An s-Plane to z-Plane Mapping Example
While surfing around the Internet recently I encountered the 's-plane to z-plane mapping' diagram shown in Figure 1. At first I thought the diagram was neat because it's a good example of the old English idiom: "A picture is worth a thousand words." However, as I continued to look at Figure 1 I began to detect what I believe are errors in the diagram.
Reader, please take a few moments to see if you detect any errors in Figure 1.
...The Most Interesting FIR Filter Equation in the World: Why FIR Filters Can Be Linear Phase
This blog discusses a little-known filter characteristic that enables real- and complex-coefficient tapped-delay line FIR filters to exhibit linear phase behavior. That is, this blog answers the question:
What is the constraint on real- and complex-valued FIR filters that guarantee linear phase behavior in the frequency domain?I'll declare two things to convince you to continue reading.
Declaration# 1: "That the coefficients must be symmetrical" is not a correct
Signal Processing Contest in Python (PREVIEW): The Worst Encoder in the World
When I posted an article on estimating velocity from a position encoder, I got a number of responses. A few of them were of the form "Well, it's an interesting article, but at slow speeds why can't you just take the time between the encoder edges, and then...." My point was that there are lots of people out there which take this approach, and don't take into account that the time between encoder edges varies due to manufacturing errors in the encoder. For some reason this is a hard concept...
New Code Sharing Section & Reward Program for Contributors!
UPDATE (11/02/2010): The code section is now live.
UPDATE 2 (01/31/2011): The reward program has changed. A flat fee of $20 per code snippet submitted will now be paid.
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I am very happy to finally announce the imminent launch of the new code sharing section. My vision for this new section is a rich library of high quality code snippets for the DSP community, from processor specific functions to Matlab or Scilab routines, from the simplest filter...
50,000th Member Announced!
In my last post, I wrote that DSPRelated.com was about to reach the 50,000 members mark. Well, I am very happy to announce that it happened during the holidays, and the lucky person is Charlie Tsai from Taiwan. Charlie is an assistant professor in the Department of Electrical Engineering at the National Central University in Taiwan where he teaches the "Biomedical Signal Processing" class. He is also the advisor of the
Almost 50,000 Members!
I am very happy to announce that DSPRelated.com will reach the 50,000 registered members mark before the end of 2009. To celebrate this milestone, I will buy a BMW 5 to the 50,000th person to register (please make sure to confirm you email address to activate your registration). Please read the fine prints after the picture.
I am just having fun here and it's not even April's fool day. The 50,000th member won't get a BMW (I wish I could offer it!),...
DSPRelated faster than ever!
if you are visiting DSPRelated.com on a regular basis, you should observe that the site loads significantly faster in your browser than it used to, especially if you are in Europe or in Asia. The main reason for this is that I am now using Amazon's CloudFront service for the delivery of most static content on DSPRelated.com (images, javascripts, css). The cloudFront service automatically detects the location of a visitor and will deliver the static content from the server...
New Papers / Theses Section
The new 'Papers & Theses' section is now online: http://www.dsprelated.com/documents.phpThe idea is to list and organize in one place as many DSP related dissertations (PhD & Masters) and papers/articles as possible.If you are the author of a thesis or paper and would like to have it listed on DSPRelated.com, please follow these steps:- Make sure that you are allowed to share the document online (copyright).- If you don't already have one, make a 'pdf' copy of your document. ...
New Blog Section!
By now, chances are you have noticed the new blogs section (you are actually in it right now!).
Following an email I sent to the members of the site, a few weeks ago, asking for dsp engineers willing to blog here, I received around 50 propositions. I have selected an initial set of 10 bloggers (that I will soon introduce into a seperate post) and I am currently in the process of creating their accounts. Markus and Parth have already...
New Discussion Group: DSP & FPGA
I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com
As usual, it should take a few weeks before there are enough members for interesting discussions to get started.
